AD7732 Analog Devices, AD7732 Datasheet - Page 28

• Manufacturer Part Number: AD7732
• Manufacturer: Analog Devices

Specifications of AD7732

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 3.05MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7732
Multiplexer, Conversion, and
Data Output Timing
The specified conversion time includes one or two settling and
sampling periods and a scaling time.
With chopping enabled (Figure 25), a conversion cycle starts
with a settling time of 43 MCLK cycles or 44 MCLK cycles (~7
μs with a 6.144 MHz MCLK) to allow the circuits following the
multiplexer to settle. The sigma-delta modulator then samples
the analog signals and the digital filter processes the digital data
stream. The sampling time depends on FW, i.e., on the channel
conversion time register contents. After another settling of 42
MCLK cycles (~6.8 μs), the sampling time is repeated with a
reversed (chopped) analog input signal. Then, during the
scaling time of 163 MCLK cycles (~26.5 μs), the two results
from the digital filter are averaged, scaled using the calibration
registers, and written into the channel data register.
With chopping disabled (Figure 26), there is only one sampling
time preceded by a settling time of 43 MCLK cycles or
44 MCLK cycles and followed by a scaling time of
163 MCLK cycles.
Figure 26. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled
Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled
– CHANNEL 0
MULTIPLEXER
RDY
SETTLING
MULTIPLEXER
RDY
TIME
CHANNEL 0
+ CHANNEL 1
SETTLING
SAMPLING
TIME
TIME
CONVERSION TIME
Rev. A | Page 28 of 32
CONVERSION TIME
SAMPLING
SETTLING
CHANNEL 1
TIME
TIME
The RDY pin goes high during the scaling time, regardless of its
previous state. The relevant RDY bit is set in the ADC status
register and in the channel status register, and the RDY pin goes
low when the channel data register is updated and the channel
conversion cycle is finished. If in continuous conversion mode,
the part will automatically continue with a conversion cycle on
the next enabled channel.
Note that every channel can be configured independently for
conversion time and chopping mode. The overall cycle and
effective per channel data rates depend on all enabled
channel settings.
Sigma-Delta ADC
The AD7732 core consists of a charge balancing sigma-delta
modulator and a digital filter. The architecture is optimized for
fast, fully settled conversion. This allows for fast channel-to-
channel switching while maintaining inherently excellent
linearity, high resolution, and low noise.
SAMPLING
– CHANNEL 1
SCALING
TIME
TIME
SCALING
TIME