AD7732 Analog Devices, AD7732 Datasheet - Page 5

• Manufacturer Part Number: AD7732
• Manufacturer: Analog Devices

Specifications of AD7732

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 3.05MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.
ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise.
For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage
The AIN absolute voltage of ±16.5 V applies for a nominal VBIAS voltage of +2.5 V. By configuring the BIAS and RA to RD pins differently, the part will work with higher
Specifications are not production tested but guaranteed by design and/or characterization data at initial product release.
See Typical Performance Characteristics.
Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.
range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register
value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details.
AIN absolute voltages as long as the internal voltage seen by the multiplexer and the input buffer is within 200 mV to AV
BIAS, and RA to RD pins must never exceed the values specified in the Absolute Maximum Ratings.
Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ.
Outside the specified calibration range, calibration is possible but the performance may degrade.
These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
With external MCLK, MCLKOUT is disabled (the CLKDIS bit is set in the mode register).
For specified performance. Part is functional with lower V
Dynamic current charging the sigma-delta modulator input switching capacitor.
External MCLKIN = 0 V or DV
CM
Power Dissipation (Normal Mode)
AV
Power Dissipation (Standby Mode)
= Common-Mode Voltage = 0 V.
DD
+DV
DD
Current (Standby Mode)
DD
, Digital Inputs = 0 V or DV
14
15
15
Min
DD
REF
, and P0 and P1 = 0 V or AV
.
Typ
85
140
750
Rev. A | Page 5 of 32
Max
100
DD.
Unit
mW
μA
μW
DD
Test Conditions/Comments
– 300 mV. Absolute voltage for the AIN,
AD7732