AD7732 Analog Devices, AD7732 Datasheet - Page 6

• Manufacturer Part Number: AD7732
• Manufacturer: Analog Devices

Specifications of AD7732

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 3.05MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7732
TIMING SPECIFICATIONS
Table 2. (AV
noted.)
Parameter
Master Clock Range
Read Operation
Write Operation
1
2
3
4
1.6 V. See Figure 2 and Figure 3.
These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the V
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
This specification is relevant only if CS goes low while SCLK is low.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
4
5
5A
6
7
8
9
11
12
13
14
15
16
2
4
2, 3
1
DD
= 5 V ± 5%; DV
Min
1
50
500
0
0
0
0
0
50
50
0
10
0
30
25
50
50
0
DD
= 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DV
Typ
Max
6.144
60
80
60
80
80
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 6 of 32
Test Conditions/Comments
SYNC Pulsewidth
RESET Pulsewidth
CS Falling Edge to SCLK Falling Edge Setup Time
SCLK Falling Edge to Data Valid Delay
DV
DV
CS Falling Edge to Data Valid Delay
DV
DV
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
Bus Relinquish Time after SCLK Rising Edge
CS Falling Edge to SCLK Falling Edge Setup
Data Valid to SCLK Rising Edge Setup Time
Data Valid after SCLK Rising Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
DD
DD
DD
DD
of 4.75 V to 5.25 V
of 2.7 V to 3.3 V
of 4.75 V to 5.25 V
of 2.7 V to 3.3 V
OL
DD
or V
) and timed from a voltage level of
DD
OH
; unless otherwise
limits.