AD7864 Analog Devices, AD7864 Datasheet - Page 18

• Manufacturer Part Number: AD7864
• Description: High Speed, Low Power, 4-channel Simultaneous Sampling, 12-Bit ADC
• Manufacturer: Analog Devices

Specifications of AD7864

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 520kSPS
• Interface: Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7864
STANDBY MODE OPERATION
The AD7864 has a standby mode whereby the device can be
placed in a low current consumption mode (5 μA typical). The
AD7864 is placed in standby by bringing the Logic Input STBY
low. The AD7864 can be powered up again for normal opera-
tion by bringing STBY logic high. The output data buffers remain
operational while the AD7864 is in standby. This means the user
can continue to access the conversion results while the AD7864
is in standby. This feature can be used to reduce the average power
consumption in a system using low throughput rates. To reduce
average power consumption, the AD7864 can be placed in standby
at the end of each conversion sequence, that is, when BUSY
goes low and is taken out of standby again prior to the start of
the next conversion sequence. The time it takes the AD7864 to
come out of standby is referred to as the wake-up time. The
wake-up time limits the maximum throughput rate at which the
AD7864 can be operated when powering down between conver-
sion sequences. The AD7864 wakes up in approximately 2 μs when
using an external reference. The wake-up time is also 2 μs when
the standby time is less than 1 ms while using the internal refer-
ence.
standby times greater than 1 ms. Note that when the AD7864
is left in standby for periods of time greater than 1 ms, the part
requires more than 2 μs to wake up. For example, after initial
power-up using the internal reference, the AD7864 requires
6 ms to power up. The maximum throughput rate that can be
achieved when powering down between conversions is 1/(t
2 μs) = 100 kSPS, approximately. When operating the AD7864 in a
standby mode between conversions, the power savings can be
significant. For example, with a throughput rate of 10 kSPS, the
AD7864 is powered down (I
100 μs (see
Therefore, the average power consumption drops to
125/10 mW or 12.5 mW approximately.
Figure 12
Figure 13
shows the wake-up time of the AD7864 for
).
CONVST
BUSY
STBY
DD
= 5 μA) for 90 μs out of every
t
BUSY
7µs
Figure 13. Power-Down Between Conversion Sequences
100µs
BUSY
Rev. D | Page 18 of 28
+
I
DD
= 20µA
ACCESSING THE OUTPUT DATA REGISTERS
There are four output data registers, one for each of the four
possible conversion results from a conversion sequence. The
result of the first conversion in a conversion sequence is placed
in Register 1, the second result is placed in Register 2, and so
forth. For example, if the conversion sequence V
V
the results of the conversion on V
Register 1 to Register 3, respectively. The output data register
pointer is reset to point to Register 1 at the end of the first con-
version in the sequence, immediately prior to EOC going low.
At this point, the logic output, FRSTDATA, goes logic high to
indicate that the output data register pointer is addressing Reg-
ister 1. When CS and RD are both logic low, the contents of the
addressed register are enabled onto the data bus (DB0 to DB11).
IN4
Figure 12. Power-Up Time vs. Standby Time Using the On-Chip Reference
t
WAKE-UP
2µs
is selected (see the Selecting a Conversion Sequence section),
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0001
0
0.001
(Decoupled with 0.1 μF Capacitor)
t
BUSY
STANDBY TIME (Seconds)
+105°C
0.01
IN1
, V
0.1
+25°C
IN3
, and V
1
IN4
IN1
–40°C
, V
are placed in
IN3
, and
10