AD7864 Analog Devices, AD7864 Datasheet - Page 24

• Manufacturer Part Number: AD7864
• Description: High Speed, Low Power, 4-channel Simultaneous Sampling, 12-Bit ADC
• Manufacturer: Analog Devices

Specifications of AD7864

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 520kSPS
• Interface: Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7864
MICROPROCESSOR INTERFACING
The high speed parallel interface of the AD7864 allows easy
interfacing to most DSPs and microprocessors. This interface
consists of the data lines (DB0 to DB11), CS, RD, WR, EOC,
and BUSY.
AD7864 TO ADSP-2100/ADSP-2101/ADSP-2102
INTERFACE
Figure 23 shows an interface between the AD7864 and the
ADSP-210x. The CONVST signal can be generated by the
ADSP-210x or from some other external source.
shows the
signal and the address bus of the ADSP-210x. In this way, the
AD7864 is mapped into the data memory space of the
ADSP-210x.
The AD7864 BUSY line provides an interrupt to the ADSP-210x
when the conversion sequence is complete on all the selected
channels. The conversion results can then be read from the
AD7864 using successive read operations. Alternately, one can
use the EOC pulse to interrupt the ADSP-210x when the
conversion on each channel is complete when reading between
each conversion in the conversion sequence (
AD7864 is read using the following instruction:
MR0 = DM(ADC)
where MR0 is the ADSP-210x MR0 register and ADC is the
AD7864 address.
AD7864 TO TMS320C5x INTERFACE
Figure 24 shows an interface between the AD7864 and the
TMS320C5x. As with the previous interfaces, conversion can be
initiated from the TMS320C5x or from an external source, and
the processor is interrupted when the conversion sequence is
completed. The CS signal to the AD7864 is derived from the DS
signal and a decode of the address bus. This maps the AD7864
into external data memory. The RD signal from the TMS320C5x
is used to enable the ADC data onto the data bus. The AD7864
has a fast parallel bus, consequently there are no wait state
V
V
V
V
IN1
IN2
IN3
IN4
DB0 TO DB11
CS being generated by a combination of the DMS
AD7864
CONVST
Figure 23. AD7864 to ADSP-210x Interface
BUSY
WR
CS
RD
ADDRESS
DECODE
D0 TO D24
IRQn
DT1/F0
A0 TO A13
DMS
RD
WR
Figure 9
ADSP-210x
Figure 23
). The
Rev. D | Page 24 of 28
requirements. The following instruction is used to read the
conversion results from the AD7864:
IN D,ADC
where D is the data memory address and ADC is the AD7864
address.
AD7864 TO MC68HC000 INTERFACE
An interface between the AD7864 and the MC68HC000 is
shown in Figure 25. The conversion can be initiated from the
MC68HC000 or from an external source. The AD7864 BUSY
line can be used to interrupt the processor or, alternatively,
software delays can ensure that the conversion has been
completed before a read to the AD7864 is attempted. Because of
the nature of its interrupts, the MC68HC000 requires additional
logic (not shown in Figure 25) to allow it to be interrupted
correctly. For further information on MC68HC000 interrupts,
consult the Addendum to MC68000 Users Manual.
The MC68HC000 AS and R/W outputs are used to generate a
separate RD input signal for the AD7864. RD is used to drive
the MC68HC000 DTACK input to allow the processor to
execute a normal read operation to the AD7864. The conversion
results are read using the following MC68HC000 instruction:
MOVE.W ADC,D0
where D0 is the MC68HC000 D0 register and ADC is the
AD7864 address.
V
V
V
V
IN1
IN2
IN3
IN4
DB0 TO DB11
AD7864
CONVST
Figure 24. AD7864 to TMS320C5x Interface
BUSY
WR
RD
CS
ADDRESS
DECODE
DS
RD
WE
D0 TO D15
INTn
PA0
A0 TO A13
TMS320C5x