ADUC847 Analog Devices, ADUC847 Datasheet - Page 48

• Manufacturer Part Number: ADUC847
• Description: Precision Analog Microcontroller: 12MIPS 8052 Flash MCU + 10-Ch 24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC847

• Mcu Core: 8052
• Mcu Speed (mips): 12
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 10
• Other: PWM

ADuC845/ADuC847/ADuC848
NONVOLATILE FLASH/EE MEMORY OVERVIEW
The ADuC845/ADuC847/ADuC848 incorporate Flash/EE
memory technology on-chip to provide the user with nonvolatile
in-circuit reprogrammable code and data memory space.
Like EEPROM, flash memory can be programmed in-system at
the byte level, although it must first be erased, in page blocks.
Thus, flash memory is often and more correctly referred to as
Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density, and low cost. The Flash/EE memory
technology allows the user to update program code space in-
circuit, without needing to replace onetime programmable
(OTP) devices at remote operating nodes.
Flash/EE Memory on the ADuC845, ADuC847, ADuC848
The ADuC845/ADuC847/ADuC848 provide two arrays of
Flash/EE memory for user applications—up to 62 kbytes of
Flash/EE program space and 4 kbytes of Flash/EE data memory
space. Also, 8-kbyte and 32-kbyte program memory option re
a
62-kbyte option; however, simil protocols and procedures are
applicable to the 32-kbyte and 8-kbyte options unless otherwise
noted, provided that the difference in memory size is taken into
account.
The 62 kbytes Flash/EE code space are provided on-chip to
facilitate code execution without any external discrete ROM
d
in-circuit, using the serial download mode provided, using
conventional thi
user-defined protocol in user download (UL
The 4-kbyte Flash/EE data memory space can be used as a
general-purpose, nonvolatile scratchpad area. User access to
this area is via a group of seven SFRs. This space can be
programmed at a byte level, although it must first be erase
4-byte pages.
vailable. All examples and references in this datasheet use the
evice requirements. The program memory can be programmed
SPACE EFFICIENT/
DENSITY
TECHNOLOGY
Figure 26. Flash/EE Memory Development
rd party memory programmers, or via any
EPROM
FLASH/EE MEMO
TECHNOLOGY
ar
RY
TECHNOLOGY
REPROGRAMMABLE
EEPROM
IN-CIRCUIT
OAD) mode.
d in
s a
Rev. B | Page 48 of 108
,
All the following sections use the 62-kbyte program space as an
example when referring to program and ULO
64-kbyte part, t
program space, that is, from 56 kbytes to 62 kbytes. For the
32-kbyte part, the ULOAD space moves to the top 8 kbytes of th
on-chip program memory, that is., from 24 kbytes to 32 kbytes.
No ULOAD mode is available on the 8-kbyte part since the
bootload area on the 8-kbyte part is 8 kbytes long, so no us
user program space remains. The kernel still resides in the
protected area from
Flash/EE Memory Reliability
The Flash/EE program and data memory arrays on the
ADuC845/ADuC847/ADuC848 are fully qualified for two key
Flash/EE memory characteristics: Flash/EE memory cycling
endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four indepen
sequential events:
1.
2.
3.
4.
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 00H to FFH until a first
fail is recorded, signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in the Specificatio
ADuC848 Flash/EE memory endurance qualification has been
carried out in accordance with JEDEC Specification A117
the industrial temperature range of –40°C, +25°C, +85°C,
+125°C. (The LFCSP package is qualified to +85°C only.) The
results allow the specification of a minimum endurance figur
over supply and temperature of 100,000 cyc
figure of 700,000 cycles being typical of operation at 25°C.
Retention is the ability of the Flash/EE memory to retain its
programmed data over time. Again, the parts have been qualified
in accordance with the formal JEDEC Retention Lifetime Specifi-
cation (A117) at a specific junction temperature (T
part of this qualification procedure, the Flash/EE memory is
cycled to its specified endurance limit described previously,
before data retention is characterized. This means that the
Flash/EE memory is guaranteed to retain its data for its full
specified retention lifetime every time the Flash/EE memory is
reprogrammed. It should also be noted that retention lifetime,
based on an activation energy of 0.6 eV, derates with T
in Figure 27.
Initial page erase sequence
Read/verify sequence
Byte program sequence
Second read/verify sequence
he ULOAD area takes up the top 6 kbytes of the
62 kbytes to 64 kbytes.
ns table, the ADuC845/ADuC847/
les, with an endurance
AD mode. For the
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= 55°C). As
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