ADUC847 Analog Devices, ADUC847 Datasheet - Page 68

• Manufacturer Part Number: ADUC847
• Description: Precision Analog Microcontroller: 12MIPS 8052 Flash MCU + 10-Ch 24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC847

• Mcu Core: 8052
• Mcu Speed (mips): 12
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 10
• Other: PWM

ADuC845/ADuC847/ADuC848
POWER SUPPLY MONITOR
The power supply monitor, once enabled, monitors the DV
and AV
supply pins drop below one of four user-selectable voltage trip
points from 2.63 V to 4.63 V. For correct operation of the power
supply monitor function, AV
2.63 V. Monitor function is controlled via the PSMCON SFR. If
enabled via the IEIP2 SFR, the monitor interrupts the core by
using the PSMI bit in the PSMCON SFR. This bit is not cleared
until the failing power supply returns above the trip point for at
least 250 ms.
The monitor function allows the user to save working registers
to avoid possible data loss due to the low supply condition, and
also ensures that normal code execution does not resume until a
Table 43. PSMCON SFR Bit Designations
Bit No.
7
6
5
4, 3
2, 1
0
DD
supplies on the parts. It indicates when any of the
Name
CMPD
CMPA
PSMI
TPD1, TPD0
TPA1, TPA0
PSMEN
Description
DV
This read-only bit directly reflects the state of the DV
Read 1 indicates that the DV
Read 0 indicates that the DV
AV
This read-only bit directly reflects the state of the AV
Read 1 indicates that the AV
Read 0 indicates that the AV
Power Supply Monitor Interrupt Bit.
Set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The PSMI
bit can be used to interrupt the processor. Once CMPD and/or CMPA returns (and remains) high, a 250 ms
counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the
user. However, if either comparator output is low, it is not possible for the user to clear PSMI.
DV
A 5 V part has no valid PSM trip points. If the DV
3 V part, all relevant PSM trip points are valid. The 3 V POR trip point is 2.63 V (fixed).
These bits select the DV
TPD1
0
0
1
1
AV
TPA1
0
0
1
1
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
DD
DD
DD
DD
DD
must be equal to or greater than
Comparator Bit.
Trip Point Selection Bits. These bits select the AV
Trip Point Selection Bits.
Comparator Bit.
TPD0
0
1
0
1
TPA0
0
1
0
1
Selected DV
4.63
3.08
2.93
2.63
Selected AV
4.63
3.08
2.93
2.63
DD
trip point voltage as follows:
DD
DD
DD
DD
DD
DD
supply is above its selected trip point.
supply is below its selected trip point.
supply is above its selected trip point.
supply is below its selected trip point.
Trip Point (V)
DD
Trip Point (V)
Rev. B | Page 68 of 108
safe supply level is well established. The supply monitor is also
protected against spurious glitches triggering the interrupt
circuit.
The 5 V part has an internal POR trip level of 4.63 V, which
means that there are no usable DV
part. The 3 V part has a POR trip level of 2.63 V following a
reset and initialization sequence, allowing all relevant PSM trip
points to be used.
PSMCON—Power Supply Monitor Control Register
SFR Address:
Power-On Default:
Bit Addressable:
DD
supply falls below the 4.63 V point, the part resets (POR). For a
DD
DD
DD
comparator.
comparator.
trip point voltage as follows:
DFH
DEH
No
DD
PSM trip levels on the 5 V