ADUC847 Analog Devices, ADUC847 Datasheet - Page 76

• Manufacturer Part Number: ADUC847
• Description: Precision Analog Microcontroller: 12MIPS 8052 Flash MCU + 10-Ch 24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC847

• Mcu Core: 8052
• Mcu Speed (mips): 12
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 10
• Other: PWM

ADuC845/ADuC847/ADuC848
TCON—Timer/Counter 0 and 1 Control Register
SFR Address:
Power-On Default:
Bit Addressable:
Table 51. TCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
___________________________________________
1
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as independent registers or combined into a single 16-bit register, depending
on the timers’ mode configuration.
TH0 and TL0—Timer 0 high and low bytes.
SFR Address:
Power-On Default:
TH1 and TL1—Timer 1 high and low bytes.
SFR Address:
Power-On Default:
These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external INT0 and INT1 interrupt pins.
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
1
1
1
1
88H
00H
Yes
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or by a zero level applied to the external interrupt pin, INT1, depending on the
state of Bit IT1.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag rather than the on-chip
hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT0, depending on
the statue of Bit IT0.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag rather than the on-chip
hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
8CH and 8AH, respectively.
00H and 00H, respectively.
8DH and 8BH, respectively.
00H and 00H, respectively.
Rev. B | Page 76 of 108