ADUC847 Analog Devices, ADUC847 Datasheet - Page 77

• Manufacturer Part Number: ADUC847
• Description: Precision Analog Microcontroller: 12MIPS 8052 Flash MCU + 10-Ch 24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC847

• Mcu Core: 8052
• Mcu Speed (mips): 12
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 10
• Other: PWM

Timer/Counter 0 and 1 Operating Modes
This section describes the operating modes for Timer/Counters
0 and 1. Unless otherwise noted, these modes of operation are
the same for both Timer 0 and Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 52 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single-cycle core.
P3.2/INT0
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. TF0 can then be used to request an
interrupt. The counted input is enabled to the timer when TR0
= 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the
timer to be controlled by external input INT0 to facilitate pulse-
width measurements. TR0 is a control bit in the special function
register TCON; Gate is in TMOD. The 13-bit register consists of
all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of
TL0 are indeterminate and should be ignored. Setting the run
flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 53.
P3.2/INT
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
P3.4/T0
CORE
P3.4/T0
CLK
CORE
GATE
CLK
GATE
1
1
0
TR0
TR0
Figure 52. Timer/Counter 0, Mode 0
Figure 53. Timer/Counter 0, Mode 1
C/T = 0
C/T = 1
C/T = 0
C/T = 1
CONTROL
CONTROL
(5 BITS)
(8 BITS)
TL0
TL0
(8 BITS)
(8 BITS)
TH0
TH0
TF0
TF0
INTERRUPT
INTERRUPT
Rev. B | Page 77 of 108
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload as shown in Figure 54. Overflow from
TL0 not only sets TF0, but also reloads TL0 with the contents of
TH0, which is preset by software. The reload leaves TH0
unchanged.
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 55.
TL0 uses the Timer 0 Control Bits C/ T , Gate, TR0, INT0 , and
TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1.
Therefore, TH0 then controls the Timer 1 interrupt. Mode 3
is provided for applications requiring an extra 8-bit timer or
counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or it can still be
used by the serial interface as a baud rate generator. In fact, it
can be used in any application not requiring an interrupt from
Timer 1 itself.
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
P3.2/INT
P3.4/T0
CORE
P3.2/INT
CLK
P3.4/T0
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
GATE
CORE
CLK/12
CLK
CORE
GATE
1
0
TR1
1
0
TR0
TR0
Figure 54. Timer/Counter 0, Mode 2
Figure 55. Timer/Counter 0, Mode 3
C/T = 0
C/T = 1
C/T = 0
C/T = 1
ADuC845/ADuC847/ADuC848
CORE
CLK/12
CONTROL
CONTROL
(8 BITS)
(8 BITS)
TH0
TL0
RELOAD
(8 BITS)
(8 BITS)
TH0
TL0
TF1
TF0
TF0
INTERRUPT
INTERRUPT
INTERRUPT