ADUC847 Analog Devices, ADUC847 Datasheet - Page 54

• Manufacturer Part Number: ADUC847
• Description: Precision Analog Microcontroller: 12MIPS 8052 Flash MCU + 10-Ch 24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC847

• Mcu Core: 8052
• Mcu Speed (mips): 12
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 10
• Other: PWM

ADuC845/ADuC847/ADuC848
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is shown in Figure 33.
Features of this architecture include inherent guaranteed
monotonicity and excellent differential linearity. As shown in
Figure 33, the reference source for the DAC is user-selectable in
software. It can be either AV
the DAC output transfer function spans from 0 V to the voltage
at the AV
function spans from 0 V to the internal V
output buffer amplifier features a true rail-to-rail output stage
implementation. This means that, unloaded, each output is
capable of swinging to within less than 100 mV of both AV
and ground. Moreover, the DAC’s linearity specification (when
driving a 10 kΩ resistive load to ground) is guaranteed through
the full transfer function except Codes 0 to 48 in 0 V-to-V
mode; Codes 0 to 100; and Codes 3950 to 4095 in 0 V-to-V
mode.
Linearity degradation near ground and V
tion of the output amplifier; a general representation of its effects
(neglecting offset and gain error) is shown in Figure 34. The
dotted line indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output amplifier.
N
mode only. In 0 V-to-V
nonlinearity w ld b simila
transfer function wo d follo
showing no signs of
ote that Figure 34 represents a transfer function in 0-to-V
DD
Figure 33. Resistor String DAC Functional Equivalent
AV
V
pin. In 0 V-to-V
REF
DD
ou
th
ul
e
R
R
R
R
R
e hig
REF
mode (with V
h-end endpoint linearity error.
DD
REF
r, but the upper portion of the
w the ideal line to the end,
or V
mode, the DAC output transfer
REF
(FROM MCU)
DISABLE
. In 0 V-to-AV
OUTPUT
BUFFER
HIGH-Z
REF
DD
REF
< V
is caused by satura-
(2.5 V). The DAC
DD
14
), the lower
DD
mode,
REF
DD
DD
DD
Rev. B | Page 54 of 108
V
The endpoint nonlinearities shown in Figure 34 become worse
as a function of output loading. Most data sheet specifications
assume a 10 kΩ resistive load to ground at the DAC output. As
the output is forced to source or sink more current, the nonlinear
regions at the top or bottom, respectively, of Figure 34 become
larger. With larger current demands, this can significantly limit
output voltage swing. Figure 35 and Figure 36 illustrate this
behavior. Note that the upper trace in each of these figures is
valid only for an output range selection of 0 V to AV
to-V
nonlinearities while the reference voltage remains below the
upper trace in the corresponding figure. For example, if AV
3 V and V
loads of less than 5 mA. But around 7 mA, the upper curve in
Figure 36 drops below 2.5 V (V
higher currents, the output is not capable of reaching V
V
DD
DD
–100mV
–50mV
100mV
Figure 35. Source and Sink Current Capability with V
50mV
REF
0mV
V
Figure 34. Endpoint Nonlinearities Due to Amplifier Saturation
DD
mode, DAC loading does not cause high-side voltage
5
4
3
2
1
0
0
REF
000H
= 2.5 V, the high-side voltage is not affected by
SOURCE/SINK CURRENT (mA)
5
DAC LOADED WITH 0FFFH
DAC LOADED WITH 0000H
REF
), indicating that at these
10
REF
= AV
DD
DD
. In 0 V-
REF
15
= 5 V
FFFH
.
DD
=