TDF8599A NXP Semiconductors, TDF8599A Datasheet - Page 10

• Manufacturer Part Number: TDF8599A
• Description: The TDF8599A is a dual Bridge-Tied Load (BTL) car audio amplifier comprising anNDMOST-NDMOST output stage based on SOI BCDMOS technology
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDF8599A_2
Product data sheet
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect
of the external oscillator signal connected to pin OSCIO. Phase lock operation is also
needed to enable phase staggering, see
is enabled when the oscillator is in Slave mode by connecting two capacitors (C
C
pin SSM to pin AGND disables phase lock operation and causes the slave to directly use
the external oscillator signal. Values for C
loop bandwidth (B
corresponding values for C
Remark: C
more detailed information.
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth B
Table 7
Table 7.
OSCSET pin
R
R
R
R
C
C
Fig 8.
PLL_p
osc
osc
osc
osc
PLL_p
PLL_s
> 26 k
> 26 k
= 0
= 0
a. Off
) and a resistor (R
lists all oscillator modes.
=
=
Phase lock operation
Oscillator modes
------------------------------ - F
R
------------------------------ - F
R
PLL_p
PLL
PLL
100 A
0.032
0.8
PLL
is only needed when
OSCIO pin
output
output
input
input
B
PLL
B
PLL
PLL
) of the PLL. R
Rev. 02 — 30 June 2009
PLL
OSCSET
SSM
001aai776
PLL
PLL_s
) between pin SSM and pin AGND (see
should be 100
I
2
C-bus controlled dual channel class-D power amplifier
SSM pin
C
shorted to pin AGND
C
shorted to pin AGND
and C
SSM
PLL
PLL
+ R
to pin AGND
1
PLL_p
PLL
is given by: R
4
Section 8.4.2 on page
PLL_s
to pin AGND
phase shift is selected. See
are given by
, C
f
SSM
PLL_p
.
(1) Only needed when
100 A
b. On
PLL
PLL
selected
and R
Oscillator modes
master, spread spectrum
master, no spread spectrum
slave, PLL enabled
slave, PLL disabled
= 8.4
Equation 3
PLL
OSCSET
SSM
13. Phase lock operation
B
depend on the desired
PLL
Figure
TDF8599A
and
R PLL
C PLL_s
1
© NXP B.V. 2009. All rights reserved.
Section 8.4.2
4
. The
Equation
phase shift is
8). Connecting
C PLL_p (1)
001aai777
PLL_s
4:
10 of 54
for
and
(3)
(4)