LPC1759FBD80 NXP Semiconductors, LPC1759FBD80 Datasheet - Page 14
Manufacturer Part Number
The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
Product data sheet
7.6 Memory map
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permitted by the region setting, will cause the Memory Management Fault
exception to take place.
The LPC1759/58/56/54/52/51 incorporate several distinct memory regions, shown in the
user program viewpoint following reset. The interrupt vector area supports address
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 March 2011
shows the overall map of the entire address space from the
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
14 of 74