XA-C3 NXP Semiconductors, XA-C3 Datasheet - Page 49

• Manufacturer Part Number: XA-C3
• Description: The XA-C3 is a member of the Philips XA (eXtended Architecture) family of high-performance 16-bit single-chip microcontrollers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 23. Allowable Message Buffer Sizes
MNBLR
The Buffer Location Register holds the least significant 16 bits of the
object’s message buffer base address. The upper 8 bits of the
24–bit address, for all Message Objects, are specified by the
contents of MBSR. Thus, the message buffers for all Message
Objects must reside within the same 64Kbyte segment.
For any message buffer which is to be mapped into the on–chip
message buffer RAM (XRAM), MnBLR bits [15:9] must match
XRAMBASE bits [15:9].
Important constraints:
Note: Message buffer logical address spaces must always adhere to
the above constraints. However, there are at least two cases in
which the User must initialize the MnBLR register such that it does
not point to the actual base location of the logical buffer space when
reception begins. For details, please see sections entitled
Fragmented Messages in OSEK on page 44 and Fragmented
Messages in CANopen on page 44.
Message Assembly
The DMA will transfer the accepted message from the pre–buffer to
the message buffer area one word at a time, starting from the
address pointed to by [MBXSR][MnBLR]. Every time DMA transfers
a byte or word, it has to request the bus. Once granted, it will write
data from the 13 byte receive pre–buffer to memory. The DMA will
keep requesting the bus, writing message data sequentially to the
2000 Jan 25
256–byte buffers must be located at a 256–byte boundary
(MnBLR[7:0] = 00000000b)
128–byte buffers must be located at a 128–byte boundary
(MnBLR[6:0] = 0000000b)
2–byte buffers must be located at a 2–byte boundary (MnBLR[0] =
0)
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
15
BSZ.2
0
0
0
0
1
1
1
1
14
BSZ.1
0
0
1
1
0
0
1
1
13
12
BSZ.0
0
1
0
1
0
1
0
1
11
a15 – a0 of object n message buffer base address
Buffer Size
128 Bytes
256 Bytes
10
16 Bytes
32 Bytes
64 Bytes
2 Bytes
4 Bytes
8 Bytes
9
8
42
The User should bear in mind that only data bytes and (for Rx only)
a single byte of frame or byte–count information is stored in the
message buffer. Space does not need to be allocated for headers,
Fragmentation information, etc. See the Rx memory buffer images
below.
MnBLR: Message n Buffer Location Register
7
memory until the whole frame is transferred. When DMA has
successfully transferred data from an incoming CAN message to
memory, the contents of the receive buffer will depend on whether
the message was non–Fragmented (single frame) or Fragmented.
Non–Fragmented Message Assembly
Since Masking is permitted on the 11– or 29–bit CAN Identifier for
Message Objects with FRAG = 0, the complete CAN ID for the
incoming message is written into the MnMIDH and MnMIDL
registers when the DMA has completed. This will permit the User
application to see the exact CAN identifier which resulted in the
match.
As a result of the above mechanism, the contents of MnMIDH and
MnMIDL can change every time an incoming frame is accepted.
Since the incoming frame has to pass the Match before it can be
accepted, only the bits that are Masked out will change. Therefore,
the criteria for Match and Mask will not change as a result of an
accepted incoming frame (see Figure 38).
Address: MMR base + nAh
Access: Read, write. Word access only.
Reset Value: xxxxh
Figure 38. Memory Image for Non–Fragmented Messages
6
Data byte 1
Data byte 2
Data byte 3
Data byte 4
Data byte 5
Data byte 6
Data byte 7
Data byte 8
Frame Info
5
4
3
Direction of increasing
Preliminary specification
2
address
dd
1
XA-C3
0