XA-C3 NXP Semiconductors, XA-C3 Datasheet - Page 64

• Manufacturer Part Number: XA-C3
• Description: The XA-C3 is a member of the Philips XA (eXtended Architecture) family of high-performance 16-bit single-chip microcontrollers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
XRAMB
XRE
MIFCNTL
WAITD
BUSD
MIFBTRL
MIFBTRH (Memory Interface Bus Timing Register High, MMR)
MIFBTRH
Note: The two MMRs MIFBTRL and MIFBTRH are not to be
confused with the two SFRs BTRL and BTRH, which control the
operation of the BIU, not the MIF. In order for the MIF to function
properly, the contents of BTRL and BTRH have to be set at a fixed
configuration on reset, by User application software, similar to the
treatment for the XA-SCC MIF.
Bus Arbitration
Bus arbitration is done on an “alternate” policy. After a DMA bus
access, the CPU will get the bus if requested. After a CPU bus
SPICFG
SPCP
Rsvd
SPC3 – SPC0
SPIDATA
SPICS (MMR)
2000 Jan 25
Address: MMR base + 294h
Address: MMR base + 263h
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
SPCP
WM1
DW1
7
7
–
7
7
7
7
XRAM Enable bit, resets to ‘0’.
0 = XRAM disabled
1 = XRAM enabled
Wait Disable
0 = Wail enabled
1 = Wait disabled
External Access Disable
0 = enable
1 = disable
SPICLK Polarity
0 = inverted SPICLK
1 = normal SPICLK
Reserved bits, only write zeros.
SPICLK timing
WM0
Rsvd
DW0
6
6
–
6
6
6
6
ALEW
DWA1
Rsvd
5
5
–
5
5
5
5
a15 – a9 of XRAM Base Address
WAITD
DWA0
Rsvd
4
4
4
–
4
4
4
Data
57
MIF Control and Configuration Registers
MIFCNTL (SFR)
MIFBTRL (Memory Interface Bus Timing Register Low, MMR)
access, the DMA will get the bus if requested. A burst access from
the CPU cannot be interrupted by a DMA bus access.
SPI Port
The on–chip SPI Port uses the following Memory Mapped Registers:
SPICFG (MMR)
SPICLK = (CClk) / 4 (SPICFG[3:0] + 1)
SPIDATA (MMR)
BUSD
Address: SFR 495h
Address: MMR base + 292h
Access: Read, write, byte or word
Reset value: EFh
Access: Read, write, byte or word
Reset value: FFh
Address: MMR base + 260h
Access: Read, write, byte or word
Reset value: 00h
SPC3
Address: MMR base + 262h
Access: Read, write, byte or word
Reset value: 00h
Access: Read, write, byte or word
Reset value: 00h
CR1
DR1
3
3
3
3
3
3
SPC2
CR0
DR0
2
2
–
2
2
2
2
CRA1
DRA1
SPC1
1
1
–
1
1
1
1
Preliminary specification
XA-C3
CRA0
DRA0
SPC0
XRE
0
0
–
0
0
0
0