XA-H4 NXP Semiconductors, XA-H4 Datasheet - Page 15

• Manufacturer Part Number: XA-H4
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1999 Sep 24
USART3 Write Register 0
USART3 Write Register 1
USART3 Write Register 2
USART3 Write Register 3
USART3 Write Register 4
USART3 Write Register 5
USART3 Write Register 6
USART3 Write Register 7
USART3 Write Register 8
USART3 Write Register 9
USART3 Write Register 10
USART3 Write Register 11
USART3 Write Register 12
USART3 Write Register 13
USART3 Write Register 14
USART3 Write Register 15
USART3 Write Register 16
USART3 Write Register 17
USART3 Read Register 0
USART3 Read Register 1
USART3 Read Register 3
USART3 Read Register 6
USART3 Read Register 7
USART3 Read Register 8
USART3 Read Register 10
DMA Control Register Ch.0 Rx
FIFO Control & Status Reg Ch.0 Rx
Segment Register Ch.0 Rx
Buffer Base Register Ch.0 Rx
Buffer Bound Register Ch.0 Rx
Address Pointer Reg Ch.0 Rx
Byte Count Register Ch.0 Rx
Data FIFO Register Ch.0 Lo Rx
Data FIFO Register Ch.0 Hi Rx
DMA Control Register Ch.1 Rx
FIFO Control & Status Register Ch.1 Rx
Segment Register Ch. 1 Rx
Single-chip 16-bit microcontroller
Reserved
Reserved
Reserved
MMR Name
or Read Only
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Size
USART3 Registers
16
16
16
16
16
Rx DMA Registers
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8F6-8FEh
Address
Offset
8CAh
8CCh
8CEh
8DAh
8DCh
8DEh
8ECh
8C0h
8C2h
8C4h
8C6h
8C8h
8D0h
8D2h
8D4h
8D6h
8D8h
8E8h
8EAh
8E0h
8E2h
8E4h
8E6h
8EEh
10Ah
10Ch
10Eh
8F0h
8F2h
8F4h
100h
101h
102h
104h
106h
108h
110h
111h
112h
15
Command register
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx miscellaneous parameters & mode
Tx parameter and control
HDLC/SDLC address field or Match Character 0
HDLC/SDLC flag or Match Character 1
Transmit Data Buffer
Master Interrupt control
Miscellaneous Tx/Rx control register
Clock Mode Control
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Miscellaneous Control bits
External/Status interrupt control
Match Character 2 (WR16)
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status/residue code
Interrupt Pending Bits
SDLC byte count low register
SDLC byte count high and FIFO status
Receive Buffer
Loop/clock status
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
10Ch = Byte 0 = older,
10Dh = Byte 1 = younger
10Eh = Byte 2 = older,
10Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64 k data segment
Description
Preliminary specification
XA-H4
Reset
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
–
00h
00h
00h
00h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
Value