XA-H4 NXP Semiconductors, XA-H4 Datasheet - Page 30

• Manufacturer Part Number: XA-H4
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

1. On a 16-bit bus, if only one byte is being written, then only one of BLE_CASL or BHE_CASH will go active. On an 8-bit bus, BLE_CASL
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all generic reads and fetches, in order to
3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active.
4. To meet hold time, EDO DRAM drives data onto the bus until OE rises, or until a new falling edge of CAS.
5. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load
6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H4 User Manual for details.
7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus,
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (3.3 V +/–10%)
V
NOTE:
1999 Sep 24
DD
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Single-chip 16-bit microcontroller
t
CPWH
CHCX
CHAH
CHSH
CODH
CPWL
AHDR
OHDE
CHDV
SHDH
CLCX
CLCH
CHCL
CHAV
CHSL
DVSL
SHAH
AVSL
t
CLRL
goes active for all (odd or even address) accesses. BHE_CASH will not go active during any accesses on an 8-bit bus.
meet hold time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address
changes. On all FPM DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive).
capacitance for all outputs (except ClkOut) = 80 pF.
A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch.
t
t
t
t
F
DIS
DIH
WS
WH
t
RP
= 3.3 V +/– 10%; T
C
C
7, 8, 10, 11, 12, 14, 15,
7, 8, 10, 14, 15, 17, 18
11, 12, 17, 18, 19, 20
8, 10, 11, 14, 18
17, 18, 19
Fig re
Figure
11, 19
16, 20
7, 14
9, 13
9, 16
9, 16
amb
23
23
23
23
23
All
All
All
All
All
24
22
21
25
25
= –40 C to +85 C (industrial)
System Clock (internally called CClk) Frequency
System Clock Period = 1/FC
XTALIN High Time
XTALIN Low Time
XTALIN Rise Time
XTALIN Fall Time
Address Valid to Strobe low
Address hold after ClkOut rising edge
Delay from ClkOut rising edge to address valid
Delay from ClkOut rising edge to Strobe High
Delay from ClkOut rising edge to Strobe Low
ClkOut Duty Cycle High (into 40 pF max.)
CAS Pulse Width High
CAS Pulse Width Low
RAS precharge time, thus minimum RAS high time
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at
end of Data Read Cycle (not code fetch)
Data In Valid setup to ClkOut rising edge
Data In Valid hold after ClkOut rising edge
OE high to XA Data Bus Driver Enable
Clock High to Data Valid
Data Valid prior to Strobe Low
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
CAS low to RAS low
WAIT setup (stable high or low) prior to ClkOut rising edge
WAIT hold (stable high or low) after ClkOut rising edge
Data Read and Instruction Fetch Cycles
All DRAM Cycles
Data Read Only
Write Cycles
All Cycles
Wait Input
Refresh
Parameter
Parameter
30
9
2
9
9
8
(n * t
t
t
t
t
t
t
t
t
t
t
t
t
CHCX
C
33.33
C
C
C
C
C
C
C
C
C
C
Min
C
* 0.5
* 0.4
32
25
– 25
– 21
– 12
– 10
– 12
– 19
– 23
– 25
– 15
0
–
–
1
–
1
1
0
–
0
) – 16
–7
Limits
Preliminary specification
8
t
CHCX
Max
30
30
28
25
30
–
–
–
5
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XA-H4
+3
Unit
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns