XA-H4 NXP Semiconductors, XA-H4 Datasheet - Page 3
XA-H4
Manufacturer Part Number
XA-H4
Description
The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
Manufacturer
NXP Semiconductors
Datasheet
1.XA-H4.pdf
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1. Can be used as additional counters if not needed as BRGs.
K=30 MHz, F = (–40 to +85), BE = LQFP
Philips Semiconductors
Table 1. XA-H3 and XA-H4 features comparison
NOTE:
ORDERING INFORMATION
NOTE
1999 Sep 24
Maximum External Memory
(Harvard Memory Mode)
Maximum External Memory
(Unified Memory Mode)
Memory Controller supports both Harvard and Unified architectures
De-multiplexed Address/Data Bus
DRAM Controller
DMA Channels
Dynamic Bus Sizing
Dynamic Bus Timing
Programmable Chip Selects
General Purpose IO Pins
Potential Interrupt Pins
Interrupts (programmable priority)
Two Counter/Timers plus Watchdog
Baud Rate Generators
Serial Ports
Maximum Serial Data Rates
Match Characters
Hardware Autobaud
H4 = PXAH40KFBE
Single-chip 16-bit microcontroller
ROMless Only
1
–40 to +85 C, 100-Pin Low Profile Quad Flat Package (LQFP)
Feature
Temperature range C and Package
3
asynch to 230.4 kbps (no sync)
4 High Priority SW
9 Hardware Event
7 Standard SW
4 UARTs
XA-H3
6 MB
6 MB
Yes
Yes
Yes
Yes
Yes
No
No
No
33
16
8
6
4
Freq (MHz)
30
Package Drawing Number
(16 MB Code, 16 MB Data)
4 async chars per USART
asynch to 230.4 kbps
4 High Priority SW
9 Hardware Event
up to 230.4 kbps
7 Standard SW
sync to 1 Mbps
SOT407-1
Preliminary specification
4 USARTs
XA-H4
32 MB
16 MB
Yes
Yes
Yes
Yes
Yes
Yes
33
16
8
6
4
XA-H4
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