XA-H4 NXP Semiconductors, XA-H4 Datasheet - Page 37
XA-H4
Manufacturer Part Number
XA-H4
Description
The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
Manufacturer
NXP Semiconductors
Datasheet
1.XA-H4.pdf
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Philips Semiconductors
1999 Sep 24
Single-chip 16-bit microcontroller
ClkOut
t
CASL
D[7:0]
CHAV
RAS
OE
A
ClkOut
t
CASL
CHAV
D[7:0]
RAS
OE
1
Note 3
A
Note.
t
AVSL
1
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
RAS ADDRESS
t
t
2
AVSL
CHAH
t
CHAH
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
To meet Hold Time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 8, 10, and 12 in this example).
2
ADDR
RAS
t
CHSL
t
CHSL
t
CHSL
t
AVSL
Figure 18. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8-Bit Bus
3
3
t
AVSL
CAS ADDR
4
CAS ADDR
Figure 19. EDO DRAM Burst Code Fetch on 8-Bit Bus
EVEN
4
Even
5
t
t
t
DIS
LS Byte
CHSH
CHSL
5
6
LS Byte
t
DIS
t
t
DIH
CHSH
CAS ADDR
7
ODD
CAS ADDR
6
t
CPWH
ODD
t
Note 2
CPWL
8
37
MS Byte
Note 4
7
MS Byte
9
t
CPWH
CAS ADDR
10
EVEN
8
CAS ADDR
Even
11
LS Byte
9
LS Byte
12
Note 2
CAS ADDR
13
ODD
10
CAS ADDR
ODD
t
t
CHSH
DIH
14
Note 4
MS Byte
t
CHSH
MS Byte
11
Preliminary specification
15
t
12
CHSH
XA-H4
t
OHDE
t
SU01285
SU01286
CHSH
t
OHDE
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