STM32F407VG STMicroelectronics, STM32F407VG Datasheet

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STM32F407VG

Manufacturer Part Number
STM32F407VG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F407VG

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar

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Features
1. The WLCSP90 package will soon be available.
January 2012
Core: ARM 32-bit Cortex™-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 168 MHz,
memory protection unit, 210 DMIPS/
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
– Up to 1 Mbyte of Flash memory
– Up to 192+4 Kbytes of SRAM including 64-
– Flexible static memory controller
LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– 1.8 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
– Sleep, Stop and Standby modes
– V
3×12-bit, 2.4 MSPS A/D converters: up to 24
channels and 7.2 MSPS in triple interleaved
mode
2×12-bit D/A converters
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 168 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M4 Embedded Trace Macrocell™
Low power
Kbyte of CCM (core coupled memory) data
RAM
supporting Compact Flash, SRAM,
PSRAM, NOR and NAND memories
accuracy)
registers + optional 4 KB backup SRAM
BAT
ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM,
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
supply for RTC, 20×32 bit backup
Doc ID 022152 Rev 2
Table 1.
STM32F405xx
STM32F407xx
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
Reference
LQFP64 (10 × 10 mm)
Up to 140 I/O ports with interrupt capability
– Up to 136 fast I/Os up to 84 MHz
– Up to 138 5 V-tolerant I/Os
Up to 15 communication interfaces
– Up to 3 × I
– Up to 4 USARTs/2 UARTs (10.5 Mbit/s,
– Up to 3 SPIs (37.5 Mbits/s), 2 with muxed
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
Advanced connectivity
– USB 2.0 full-speed device/host/OTG
– USB 2.0 high-speed/full-speed
– 10/100 Ethernet MAC with dedicated DMA:
8- to 14-bit parallel camera interface up to
54 Mbytes/s
True random number generator
CRC calculation unit
96-bit unique ID
RTC: subsecond accuracy, hardware calendar
ISO 7816 interface, LIN, IrDA, modem
control)
full-duplex I
accuracy via internal audio PLL or external
clock
controller with on-chip PHY
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
supports IEEE 1588v2 hardware, MII/RMII
Device summary
STM32F405RG, STM32F405VG, STM32F405ZG
STM32F407VG, STM32F407IG, STM32F407ZG,
STM32F407VE, STM32F407ZE, STM32F407IE
2
C interfaces (SMBus/PMBus)
2
S to achieve audio class
STM32F405xx
STM32F407xx
WLCSP90
Part number
(10 × 10 mm)
UFBGA176
www.st.com
FBGA
1/167
1

Related parts for STM32F407VG

STM32F407VG Summary of contents

Page 1

... True random number generator ■ CRC calculation unit ■ 96-bit unique ID ■ RTC: subsecond accuracy, hardware calendar Table 1. Device summary Reference STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407xx STM32F407VE, STM32F407ZE, STM32F407IE Doc ID 022152 Rev 2 STM32F405xx STM32F407xx FBGA UFBGA176 WLCSP90 (10 × 10 mm) C interfaces (SMBus/PMBus) 2 ...

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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F405xx, STM32F407xx 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 6 Package characteristics . . . . . . . . . . . . . . . . . . . . ...

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STM32F405xx, STM32F407xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 47. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F405xx, STM32F407xx List of figures Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 . . . . . . . . . . . . 14 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package ...

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List of figures 2 Figure 40 slave timing diagram (Philips protocol) 2 Figure 41 master timing diagram (Philips protocol) Figure 42. USB OTG FS timings: definition of data signal rise and fall time . . . ...

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STM32F405xx, STM32F407xx Figure 87. Complete audio player solution ...

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... Introduction 1 Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. ...

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STM32F405xx, STM32F407xx 2 Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM Cortex™-M4 32-bit RISC core operating at a frequency 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which ...

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Figure 5 shows the general block diagram of the device family. Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG Flash memory in Kbytes System SRAM in Kbytes Backup FSMC memory controller No Ethernet General-purpose Advanced- Timers control ...

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Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued) Peripherals STM32F405RG Operating temperatures Package LQFP64 minimum value of 1 obtained when the device operates in the °C temperature range and PDR ...

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Description 2.1 Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pin- to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and ...

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STM32F405xx, STM32F407xx Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package Ω Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package Ω Doc ID 022152 Rev 2 Description Ω Ω 15/167 ...

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Description Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package 16/167 Ω Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx ...

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STM32F405xx, STM32F407xx 2.2 Device overview Figure 5. STM32F40x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked Doc ID 022152 Rev 2 Description 17/167 ...

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Description from TIMxCLK MHz. 2. The camera interface is available only on STM32F407xxdevices. ® 2.2.1 ARM Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. ...

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STM32F405xx, STM32F407xx 2.2.4 Embedded Flash memory The STM32F40x devices embed a Flash memory of 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data. 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy ...

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Description Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, ...

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STM32F405xx, STM32F407xx The DMA can be used with the main peripherals: 2 ● SPI and ● ● USART ● General-purpose, basic and advanced-control timers TIMx ● DAC ● SDIO ● Camera interface (DCMI) ● ADC. ...

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Description pulse width shorter than the Internal APB2 clock period 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default ...

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STM32F405xx, STM32F407xx 2.2.15 Power supply supervisor The power supply supervisor is enabled by holding PDR_ON high. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is ...

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Description V minimum value is 1 operates in the °C temperature range and PDR is disabled. There are three low-power modes: – used in the nominal regulation mode (Run) – LPR is ...

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STM32F405xx, STM32F407xx Regulator OFF This mode allows to power the device as soon as V ● Regulator OFF/internal reset ON This mode is available only on UFBGA package activated by setting BYPASS_REG and PDR_ON pins to V The ...

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Description Figure 8. Startup in regulator OFF: slow V - power-down reset risen after V 1. This figure is valid both whatever the internal reset mode (on or off). Figure 9. Startup in regulator OFF mode: fast V - power-down ...

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STM32F405xx, STM32F407xx It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC ...

Page 28

Description Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising ...

Page 29

STM32F405xx, STM32F407xx Table 3. Timer feature comparison Counter Counter Timer type Timer resolution Advanced- TIM1, 16-bit control TIM8 Up/down TIM2, 32-bit TIM5 Up/down TIM3, 16-bit TIM4 Up/down TIM9 16-bit General purpose TIM10, 16-bit TIM11 TIM12 16-bit TIM13, 16-bit TIM14 TIM6, ...

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Description General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 3 for differences). ● TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 ...

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STM32F405xx, STM32F407xx SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ...

Page 32

Description Table 4. USART feature comparison USART Standard Modem LIN name features (RTS/CTS) USART1 X X USART2 X X USART3 X X UART4 X - UART5 X - USART6 X X 2.2.23 Serial peripheral interface (SPI) The STM32F40x feature up ...

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STM32F405xx, STM32F407xx 2.2.25 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I achieve error-free I performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I disabling the main PLL (PLL) used ...

Page 34

Description The STM32F407xx includes the following features: ● Supports 10 and 100 Mbit/s rates ● Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F46x reference manual for details) ● Tagged MAC frame support ...

Page 35

STM32F405xx, STM32F407xx The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that ...

Page 36

Description 2.2.34 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of ...

Page 37

STM32F405xx, STM32F407xx Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and ...

Page 38

Pinouts and pin description 3 Pinouts and pin description Figure 10. STM32F40x LQFP64 pinout 38/167 ...

Page 39

STM32F405xx, STM32F407xx Figure 11. STM32F40x LQFP100 pinout Doc ID 022152 Rev 2 Pinouts and pin description 39/167 ...

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Pinouts and pin description Figure 12. STM32F40x LQFP144 pinout 40/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx ...

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STM32F405xx, STM32F407xx Figure 13. STM32F40x LQFP176 pinout Doc ID 022152 Rev 2 Pinouts and pin description 41/167 ...

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Pinouts and pin description Figure 14. STM32F40x UFBGA176 ballout Table 5. Legend/abbreviations used in the pinout table Name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after Pin name reset is the same ...

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STM32F405xx, STM32F407xx Table 5. Legend/abbreviations used in the pinout table (continued) Name Abbreviation Alternate Functions selected through GPIOx_AFR registers functions Additional Functions directly selected/enabled through peripheral registers functions Definition Doc ID 022152 Rev 2 Pinouts and pin description 43/167 ...

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Pinouts and pin description Table 6. STM32F40x pin and ball definitions Pin number Pin name (function after reset PE2 - PE3 - PE4 - ...

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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset PF6 - - ...

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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset) PA0-WKUP (PA0 PA1 PA2 - - ...

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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset PA7 PC4 PC5 ...

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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset PE10 - 42 64 P10 74 PE11 - 43 65 ...

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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset K12 89 PH12 - - - H12 J12 P12 92 ...

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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset M15 101 PD13 - - 83 - 102 J13 103 ...

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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset 100 F15 119 PA8 42 68 101 E15 120 PA9 43 69 102 D15 121 PA10 44 70 103 C15 122 ...

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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset) PA14 49 76 109 A14 137 (JTCK-SWCLK) PA15 50 77 110 A13 138 (JTDI 111 B14 139 PC10 52 ...

Page 53

STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset 125 B10 153 PG10 - - 126 B9 154 PG11 - - 127 B8 155 PG12 - - 128 A8 156 ...

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... Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. ...

Page 55

STM32F405xx, STM32F407xx 5. If the device is delivered in an UFBGA176 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Doc ID 022152 Rev 2 Pinouts ...

Page 56

Table 7. Alternate function mapping AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 TIM2_CH1 PA0 TIM 5_CH1 TIM8_ETR TIM2_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 TIM2_CH1 PA5 TIM8_CH1N TIM2_ETR PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN ...

Page 57

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N PC0 PC1 PC2 PC3 PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 PC9 MCO2 TIM3_CH4 TIM8_CH4 PC10 PC11 ...

Page 58

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PD15 TIM4_CH4 PE0 TIM4_ETR PE1 PE2 TRACECLK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 TIM9_CH1 PE6 TRACED3 TIM9_CH2 PE7 TIM1_ETR PE8 TIM1_CH1N PE9 TIM1_CH1 PE10 TIM1_CH2N ...

Page 59

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 ...

Page 60

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PH15 TIM8_CH3N PI0 TIM5_CH4 PI1 PI2 TIM8_CH4 PI3 TIM8_ETR PI4 TIM8_BKIN PI5 TIM8_CH1 PI6 TIM8_CH2 PI7 TIM8_CH3 PI8 PI9 PI10 PI11 AF4 AF5 AF6 AF7 ...

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STM32F405xx, STM32F407xx 4 Memory map The memory map is shown in Figure 15. Memory map Figure 15. Doc ID 022152 Rev 2 Memory map 61/167 ...

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Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

Page 63

STM32F405xx, STM32F407xx 5.1.6 Power supply scheme Figure 18. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate ...

Page 64

Electrical characteristics 5.1.7 Current consumption measurement Figure 19. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9: Current characteristics, and permanent damage to the device. These are stress ratings only and ...

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STM32F405xx, STM32F407xx Table 9. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...

Page 66

Electrical characteristics Table 11. General operating conditions (continued) Symbol Parameter V When the internal regulator is ON, CAP1 V and V CAP_1 CAP_2 connect a stabilization capacitor. When the internal regulator is OFF V CAP2 (BYPASS_REG connected ...

Page 67

STM32F405xx, STM32F407xx Table 12. Limitations depending on the operating power supply range Maximum Operating power ADC supply operation range frequency (f 16 MHz with Conversion V =1 time up to (2) 2.1 V memory wait 1.2 Msps 18 ...

Page 68

Electrical characteristics 5.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor C the VCAP1/VCAP2 pins. C Figure 20. External capacitor C 1. Legend: ESR is the equivalent series resistance. Table 13. VCAP1/VCAP2 operating ...

Page 69

STM32F405xx, STM32F407xx 5.3.5 Embedded reset and power control block characteristics The parameters given in temperature and V Table 16. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (3) V PVD hysteresis PVDhyst Power-on/power-down ...

Page 70

Electrical characteristics Table 16. Embedded reset and power control block characteristics (continued) Symbol Brownout level 1 V BOR1 threshold Brownout level 2 V BOR2 threshold Brownout level 3 V BOR3 threshold 1.2 V domain V 12 voltage (3) V BOR ...

Page 71

STM32F405xx, STM32F407xx Typical and maximum current consumption The MCU is placed under the following conditions: ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled except explicitly mentioned. ● ...

Page 72

Electrical characteristics 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. Table 18. Typical and maximum current consumption in Run mode, code with data processing running from Flash ...

Page 73

STM32F405xx, STM32F407xx Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running ...

Page 74

Electrical characteristics Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running ...

Page 75

STM32F405xx, STM32F407xx Table 19. Typical and maximum current consumption in Sleep mode Symbol Parameter External clock all peripherals enabled Supply current Sleep mode External clock peripherals disabled 1. Based on characterization, tested in production ...

Page 76

Electrical characteristics Table 20. Typical and maximum current consumptions in Stop mode Symbol Parameter Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed Supply current oscillator OFF (no independent watchdog) in Stop mode with main Flash in ...

Page 77

STM32F405xx, STM32F407xx Table 22. Typical and maximum current consumptions in V Symbol Parameter Backup SRAM ON, low-speed oscillator and RTC ON Backup Backup SRAM OFF, low-speed I domain supply oscillator and RTC ON DD_VBAT current Backup SRAM ON, RTC OFF ...

Page 78

Electrical characteristics Figure 26. Typical V current consumption (LSE and RTC ON/backup RAM ON) BAT I/O system current consumption The current consumption of the I/O system has two components: static ...

Page 79

STM32F405xx, STM32F407xx voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where I is the current sunk by a switching I/O to charge/discharge the capacitive load ...

Page 80

Electrical characteristics Table 23. Switching output I/O current consumption Symbol Parameter I/O switching I DDIO current the PCB board capacitance including the pad pin This test is performed by cutting the LQFP package pin ...

Page 81

STM32F405xx, STM32F407xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● At startup, all I/O pins are configured as analog pins by firmware. ● All peripherals are disabled unless otherwise ...

Page 82

Electrical characteristics Table 24. Peripheral current consumption (continued) Peripheral AHB3 APB1 82/167 (1) 168 MHz FSMC TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 PWR USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 (2) SPI2/I2S2 0.17/0.16 (2) SPI3/I2S3 0.16/0.14 CAN1 ...

Page 83

STM32F405xx, STM32F407xx Table 24. Peripheral current consumption (continued) Peripheral APB2 1. HSE oscillator with 4 MHz crysta) and PLL are on. 2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 3. EN1 ...

Page 84

Electrical characteristics 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 26. High-speed external user clock ...

Page 85

STM32F405xx, STM32F407xx Figure 27. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 28. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...

Page 86

Electrical characteristics Table 28. HSE 4-26 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F Recommended load capacitance C versus equivalent serial resistance of the crystal (R i HSE driving current 2 g Oscillator transconductance m (4) ...

Page 87

STM32F405xx, STM32F407xx Table 29. LSE oscillator characteristics (f Symbol R Feedback resistor F Recommended load capacitance (3) C versus equivalent serial resistance of the crystal (R I LSE driving current 2 g Oscillator Transconductance m (5) t startup time SU(LSE) ...

Page 88

Electrical characteristics 5.3.9 Internal clock source characteristics The parameters given in ambient temperature and V High-speed internal (HSI) RC oscillator Low-speed internal (LSI) RC oscillator Table 30. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC ...

Page 89

STM32F405xx, STM32F407xx Figure 31. ACC 5.3.10 PLL characteristics The parameters given in temperature and V Table 32. Main PLL characteristics Symbol Parameter (1) f PLL input clock PLL_IN f PLL multiplier output clock PLL_OUT 48 MHz PLL multiplier output f ...

Page 90

Electrical characteristics Table 32. Main PLL characteristics (continued) Symbol Parameter Cycle-to-cycle jitter Period Jitter (3) Jitter Main clock output (MCO) for RMII Ethernet Main clock output (MCO) for MII Ethernet Bit Time CAN jitter (4) I PLL power consumption on ...

Page 91

STM32F405xx, STM32F407xx Table 33. PLLI2S (audio PLL) characteristics Symbol Parameter PLLI2S power consumption on (5) I DD(PLLI2S PLLI2S power consumption on (5) I DDA(PLLI2S) V DDA 1. TBD stands for “to be defined”. 2. Take care of using ...

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Electrical characteristics 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 34. SSCG parameters constraint Symbol f Mod md MODEPER * INCSTEP 1. Guaranteed by design, not ...

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STM32F405xx, STM32F407xx Figure 32 and Figure 33 down spread modes, where PLL_OUT T is the modulation period. mode md is the modulation depth. Figure 32. PLL output clock waveforms in center spread mode Figure 33. PLL output ...

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Electrical characteristics 1. TBD stands for “to be defined”. Table 36. Flash memory programming Symbol t Word programming time prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ...

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STM32F405xx, STM32F407xx Table 37. Flash memory programming with V Symbol t Double word programming prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ...

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Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in defined in application note AN1709. Table 39. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce ...

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STM32F405xx, STM32F407xx Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC standard which specifies the test board and the pin loading. Table 40. EMI characteristics Symbol Parameter V = 3.3 V, ...

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Electrical characteristics Static latchup Two complementary static tests are required on six parts to assess the latchup performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and ...

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STM32F405xx, STM32F407xx 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 44. I/O static characteristics Symbol Parameter V Input low level voltage IL (2) TTa/TC I/O input ...

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Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, ...

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STM32F405xx, STM32F407xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 46, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 11. Table 46. I/O AC ...

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Electrical characteristics Table 46. I/O AC characteristics OSPEEDRy [1:0] bit Symbol (1) value F Maximum frequency max(IO)out 11 Output high to low level fall t f(IO)out time Output low to high level rise t r(IO)out time Pulse width of external ...

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STM32F405xx, STM32F407xx 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology connected to a permanent pull-up resistor, R (see PU Unless otherwise specified, the parameters given in performed under the ambient temperature and V in ...

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Electrical characteristics 5.3.18 TIM timer characteristics The parameters given in Refer to Section 5.3.16: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 48. Characteristics of TIMx connected to the APB1 domain Symbol t Timer ...

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STM32F405xx, STM32F407xx Table 49. Characteristics of TIMx connected to the APB2 domain Symbol t Timer resolution time res(TIM) Timer external clock f EXT frequency on CH1 to CH4 Res Timer resolution TIM 16-bit counter clock t period when internal clock ...

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Electrical characteristics 2 Table 50 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...

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STM32F405xx, STM32F407xx 2 Figure 36 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 51. SCL frequency ( External pull-up resistance For speeds around 200 ...

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Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.16: I/O port characteristics function characteristics ...

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STM32F405xx, STM32F407xx Figure 37. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

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Electrical characteristics Figure 39. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V 110/167 ...

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STM32F405xx, STM32F407xx 2 Table 53 characteristics Symbol clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( valid time v(WS) ( hold ...

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Electrical characteristics 2 Figure 40 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...

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STM32F405xx, STM32F407xx USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 54. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested in production. ...

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Electrical characteristics Figure 42. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines V CRS Table 56. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time ...

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STM32F405xx, STM32F407xx USB HS characteristics Table 58 shows the USB HS operating voltage. Table 58. USB HS DC electrical characteristics Symbol Input level V 1. All the voltages are measured from the local ground potential. Table 59. USB HS clock ...

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Electrical characteristics Table 60. ULPI timing Control in (ULPI_DIR) setup time Control in (ULPI_NXT) setup time Control in (ULPI_DIR, ULPI_NXT) hold time Data in setup time Data in hold time Control out (ULPI_STP) setup time and hold time Data out ...

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STM32F405xx, STM32F407xx Table 63 gives the list of Ethernet MAC signals for the RMII and corresponding timing diagram. Figure 45. Ethernet RMII timing diagram RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV Table 63. Dynamics characteristics: Ethernet MAC signals for RMII Symbol t ...

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Electrical characteristics Table 64. Dynamics characteristics: Ethernet MAC signals for MII Symbol t Receive data setup time su(RXD) t Receive data hold time ih(RXD) t Data valid setup time su(DV) t Data valid hold time ih(DV) t Error setup time ...

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STM32F405xx, STM32F407xx Table 65. ADC characteristics Symbol Parameter (5) t Sampling time S (5) t Power-up time STAB Total conversion time (including (5) t CONV sampling time) Sampling rate ( MHz, and S ADC t = ...

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Electrical characteristics Equation 1: R AIN The formula above allowed for an error below 1/4 of LSB (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Table 66. ADC ...

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STM32F405xx, STM32F407xx Figure 47. ADC accuracy characteristics 1. See also Table 66. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line Total Unadjusted Error: maximum deviation between the actual and ...

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Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 49. Power supply and reference ...

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STM32F405xx, STM32F407xx 5.3.21 Temperature sensor characteristics Table 67. TS characteristics Symbol ( linearity with temperature L SENSE (1) Avg_Slope Average slope (1) V Voltage at 25 °C 25 (2) t Startup time START (3)(2) T ADC sampling time ...

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Electrical characteristics 5.3.24 DAC electrical characteristics Table 70. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (2) R Resistive load with buffer ON LOAD Impedance output with buffer ( ...

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STM32F405xx, STM32F407xx Table 70. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (3) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error ...

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Electrical characteristics Figure 51. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. ...

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STM32F405xx, STM32F407xx Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t ...

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Electrical characteristics Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NE ...

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STM32F405xx, STM32F407xx Figure 54. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 73. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...

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Electrical characteristics Figure 55. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 74. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...

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STM32F405xx, STM32F407xx Synchronous waveforms and timings Figure 56 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...

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Electrical characteristics Table 75. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low d(CLKL-NADVL) t FSMC_CLK ...

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STM32F405xx, STM32F407xx Figure 57. Synchronous multiplexed PSRAM write timings Table 76. Synchronous multiplexed PSRAM write timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK ...

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Electrical characteristics Figure 58. Synchronous non-multiplexed NOR/PSRAM read timings Table 77. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK ...

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STM32F405xx, STM32F407xx Figure 59. Synchronous non-multiplexed PSRAM write timings Table 78. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) d(CLKL-NExL d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t d(CLKL-NBLH) 1. ...

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Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 60 through provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ...

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STM32F405xx, STM32F407xx Figure 61. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID 022152 ...

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Electrical characteristics Figure 62. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 138/167 t v(NCE4_1-A) High ...

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STM32F405xx, STM32F407xx Figure 63. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 64. PC Card/CompactFlash controller ...

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Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for I/O space write access Table 79. Switching characteristics for PC Card/CF read and write cycles in attribute/common space Symbol t FSMC_Ncex low to FSMC_Ay valid v(NCEx-A) t FSMC_NCEx high to FSMC_Ax ...

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STM32F405xx, STM32F407xx Table 80. Switching characteristics for PC Card/CF read and write cycles (1)(2) in I/O space Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low ...

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Electrical characteristics Figure 66. NAND controller waveforms for read access Figure 67. NAND controller waveforms for write access 142/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx ...

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STM32F405xx, STM32F407xx Figure 68. NAND controller waveforms for common memory read access Figure 69. NAND controller waveforms for common memory write access Table 81. Switching characteristics for NAND Flash read cycles Symbol t FSMC_NOE low width w(N0E) t FSMC_D[15-0] valid ...

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Electrical characteristics Table 82. Switching characteristics for NAND Flash write cycles Symbol t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE pF. L 5.3.26 Camera interface (DCMI) timing specifications Table 83. DCMI characteristics ...

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STM32F405xx, STM32F407xx Figure 71. SD default mode Table 84 MMC characteristics Symbol Clock frequency in data transfer f PP mode - SDIO_CK/f t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time ...

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Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

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STM32F405xx, STM32F407xx Figure 72. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 86. LQFP64 – ...

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Package characteristics Figure 74. LQFP100 100-pin low-profile quad flat package outline 100 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in millimeters. ...

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STM32F405xx, STM32F407xx Figure 76. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to scale. ...

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Package characteristics Figure 78. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Seating plane Drawing is not to scale. Table 89. UFBGA176+25 - ultra thin ...

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STM32F405xx, STM32F407xx Figure 79. LQFP176 mm, 144-pin low-profile quad flat package outline C Seating plane Pin 1 identification 1. Drawing is not to scale. Table 90. LQFP176 mm, 144-pin low-profile quad ...

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Package characteristics 6.2 Thermal characteristics The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ is the package junction-to-ambient thermal resistance, in °C/W, ● JA ● P max ...

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STM32F405xx, STM32F407xx 7 Part numbering Table 92. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 405 = STM32F40x, connectivity, USB OTG FS/HS, 407= STM32F40x, connectivity, USB OTG FS/HS, camera interface, ...

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Application block diagrams Appendix A Application block diagrams A.1 Main applications versus package Table 93 gives examples of configurations for each package. Table 93. Main applications versus package for STM32F407xx microcontrollers 64 pins Config Config 1 2 OTG X X ...

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STM32F405xx, STM32F407xx A.2 Application example with regulator OFF Figure 80. Regulator OFF/internal reset ON 1. This mode is available only on UFBGA176 package. Figure 81. Regulator OFF/internal reset OFF 1. This mode is available only on UFBGA176 package. Doc ID ...

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Application block diagrams A.3 USB OTG full speed (FS) interface solutions Figure 82. USB controller configured as peripheral-only and used in Full speed mode 1. External voltage regulator only needed when building The same application can be ...

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STM32F405xx, STM32F407xx Figure 84. USB controller configured in dual mode and used in full speed mode 1. External voltage regulator only needed when building The current limiter is required only if the application has to support a ...

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Application block diagrams A.4 USB OTG high speed (HS) interface solutions Figure 85. USB controller configured as peripheral, host, or dual-mode and used in high speed mode possible to use MCO1 or MCO2 to save a crystal. ...

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STM32F405xx, STM32F407xx A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 86 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% error ...

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Application block diagrams Figure 88. Audio player solution using PLL, PLLI2S, USB and 1 crystal Figure 89. Audio PLL (PLLI2S) providing accurate I2S clock 1 MHz CLKIN /M M=1,2,3,..,64 N=192,194,..,432 160/167 PLLI2S 192 to 432 MHz PhaseC VCO /N /R ...

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STM32F405xx, STM32F407xx Figure 90. Master clock (MCK) used to drive the external audio DAC I2S_CK /I2SD 2,3,4,..,129 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 91. Master clock (MCK) ...

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Application block diagrams A.6 Ethernet interface solutions Figure 92. MII mode using a 25 MHz crystal 1. f must be greater than 25 MHz. HCLK 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 93. RMII with a ...

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STM32F405xx, STM32F407xx Figure 94. RMII with a 25 MHz crystal and PHY with PLL 1. f must be greater than 25 MHz. HCLK 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. ...

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Revision history 8 Revision history Table 94. Document revision history Date Revision 15-Sep-2011 24-Jan-2012 164/167 1 Initial release. Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and ...

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STM32F405xx, STM32F407xx Table 94. Document revision history (continued) Date Revision 24-Jan-2012 (continued) Added V12 in Table 16: Embedded reset and power control block characteristics. Updated Table 17: Typical and maximum current consumption in Run mode, code with data processing running ...

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Revision history Table 94. Document revision history (continued) Date Revision 24-Jan-2012 (continued) 166/167 Updated Table 57: USB FS clock timing parameters HS clock timing parameters Updated Table 65: ADC characteristics. Updated Table 66: ADC accuracy at f Updated Note 1 ...

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... STM32F405xx, STM32F407xx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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