STM32F407VG STMicroelectronics, STM32F407VG Datasheet - Page 105

• Manufacturer Part Number: STM32F407VG
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
• Manufacturer: STMicroelectronics

Specifications of STM32F407VG

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Rtc: subsecond accuracy, hardware calendar

STM32F405xx, STM32F407xx
5.3.19
Table 49.
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
The STM32F405xx and STM32F407xx I
standard I
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
The I
characteristics
and SCL) .
2
t
MAX_COUNT
C interface characteristics
t
COUNTER
Symbol
t
Res
res(TIM)
f
2
EXT
C characteristics are described in
TIM
2
C communication protocol with the following restrictions: the I/O pins SDA and
Characteristics of TIMx connected to the APB2 domain
Timer resolution time
Timer external clock
frequency on CH1 to CH4
Timer resolution
16-bit counter clock
period when internal clock
is selected
Maximum possible count
for more details on the input/output alternate function characteristics (SDA
Parameter
Table
Doc ID 022152 Rev 2
11.
DD
AHB/APB2
prescaler distinct
from 1, f
168 MHz
AHB/APB2
prescaler = 1,
f
APB2 = 84 MHz
f
TIMxCLK
TIMxCLK
2
Table
is disabled, but is still present.
C interface meets the requirements of the
Conditions
PCLK1
TIMxCLK
= 84 MHz
50. Refer also to
= 168 MHz
frequency and V
Table 50
=
5.95
11.9
Min
1
1
0
0
1
-
-
are derived from tests
Section 5.3.16: I/O port
Electrical characteristics
DD
f
TIMxCLK
supply voltage
65536
32768
(1)
Max
84
16
-
-
-
-
/2
t
t
t
t
TIMxCLK
TIMxCLK
TIMxCLK
TIMxCLK
105/167
MHz
MHz
Unit
ns
ns
bit