STM32F407VG STMicroelectronics, STM32F407VG Datasheet - Page 165

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STM32F407VG

Manufacturer Part Number
STM32F407VG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F407VG

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar

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STM32F405xx, STM32F407xx
Table 94.
24-Jan-2012
Date
Document revision history (continued)
(continued)
Revision
2
Added V12 in
characteristics.
Updated
mode, code with data processing running from Flash memory (ART
accelerator disabled)
consumption in Run mode, code with data processing running from
Flash memory (ART accelerator enabled) or
Figure
Updated
mode
Updated
mode
Standby
in V
Section : On-chip peripheral current
and updated
Changed f
Table 26: High-speed external user clock
Added C
characteristics.
Updated maximum PLL input clock frequency, removed related note,
and deleted jitter for MCO for RMII Ethernet typical value in
Main PLL
frequency and removed related note in
characteristics.
Updated
shipped to customers with the Flash memory erased. Updated
Table 35: Flash memory
Flash memory
Updated
characteristics.
Updated
Updated
Added t
connected to the APB1 domain
connected to the APB2
characteristics: Ethernet MAC signals for
Removed USB-IF certification in
characteristics.
Doc ID 022152 Rev 2
BAT
and removed Note 1.
and
22,
mode, and
COUNTER
in(LSE)
mode,
Table 19: Typical and maximum current consumption in Sleep
Table 20: Typical and maximum current consumptions in Stop
Table 17: Typical and maximum current consumption in Run
Section : Flash memory
Table 39: EMS
Table 53: I
Figure 43: ULPI timing diagram
characteristics. Updated maximum PLLI2S input clock
HSE_ext
Table 21: Typical and maximum current consumptions in
Figure
Table 24: Peripheral current consumption
Table 16: Embedded reset and power control block
programming.
in
Table 22: Typical and maximum current consumptions
and t
Table 27: Low-speed external user clock
23, anhd
to 50 MHz and t
Table 23: Switching output I/O current
2
S characteristics
and
MAX_COUNT
domain. Updated
characteristics, and
characteristics, and added t
Table 18: Typical and maximum current
Figure
Changes
and
Section : USB OTG FS
to specify that the devices are
r(HSE)
in
24.
consumption: modified conditions,
Table 49: Characteristics of TIMx
Table 48: Characteristics of TIMx
Table 33: PLLI2S (audio PLL)
/t
f(HSE)
and
characteristics.
RMII.
Table 63: Dynamics
Table 40: EMI
RAM. Added
Table 60: ULPI
maximum value in
Revision history
ME
and
in
consumption.
Figure
Table 36:
Note
Table 32:
timing.
165/167
2.
,

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