STM32F407VG STMicroelectronics, STM32F407VG Datasheet - Page 141

• Manufacturer Part Number: STM32F407VG
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
• Manufacturer: STMicroelectronics

Specifications of STM32F407VG

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Rtc: subsecond accuracy, hardware calendar

STM32F405xx, STM32F407xx
Table 80.
1. C
2. Based on characterization, not tested in production.
t
d(NCE4_1-NIOWR)
t
t
t
h(NCEx-NIOWR)
d(NIORD-NCEx)
h(NCEx-NIORD)
t
t
t
t
su(D-NIORD)
h(NIOWR-D)
d(NIORD-D)
t
v(NIOWR-D)
t
L
Symbol
w(NIOWR)
w(NIORD)
= 30 pF.
Switching characteristics for PC Card/CF read and write cycles
NAND controller waveforms and timings
Figure 66
provide the corresponding timings. The results shown in this table are obtained with the
following FSMC configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
In all timing tables, the
in I/O space
FSMC_NIOWR low width
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
FSMC_NCE4_1 low to FSMC_NIOWR valid
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCEx low to FSMC_NIORD valid
FSMC_NCEx high to FSMC_NIORD) valid
FSMC_NIORD low width
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0.
through
(1)(2)
Figure 69
T
Parameter
HCLK
represent synchronous waveforms, and
is the HCLK clock period.
Doc ID 022152 Rev 2
5T
5T
8T
8T
8T
HCLK
HCLK
HCLK
HCLK
HCLK
Min
9
0
-
-
-
– 1.5
–1.5
–0.5
– 2
–1
Electrical characteristics
Table 81
5T
5T
5T
HCLK
HCLK
HCLK
Max
-
-
-
-
-
-
-
+ 2.5
– 1
+ 2
and
Table 82
141/167
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns