STM32F407VG STMicroelectronics, STM32F407VG Datasheet - Page 99

• Manufacturer Part Number: STM32F407VG
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
• Manufacturer: STMicroelectronics

Specifications of STM32F407VG

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Rtc: subsecond accuracy, hardware calendar

STM32F405xx, STM32F407xx
5.3.16
Table 44.
1. If V
2. TTa = 3.3 V tolerant I/O directly connected to ADC; TC = standard 3.3 V I/O.
3. FT = 5 V tolerant.
4. With a minimum of 100 mV.
5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
8. Guaranteed by design, not tested in production.
Symbol
C
V
V
V
R
R
V
V
I
MOS/NMOS contribution
IH
IH
IO
lkg
hys
PU
PD
IL
IL
(1)
(1)
(8)
IH
maximum value cannot be respected, the injection current must be limited externally to I
Input low level voltage
TTa/TC
FT
Input low level voltage
TTa/TC I/O input high level voltage
FT I/O input high level voltage
I/O Schmitt trigger voltage hysteresis
IO FT Schmitt trigger voltage
hysteresis
I/O input leakage current
I/O FT input leakage current
Weak pull-up equivalent
resistor
Weak pull-down
equivalent resistor
I/O pin capacitance
(3)
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
I/O input high level voltage
(2)
(7)
(5)
I/O input high level voltage
Parameter
to the series resistance is minimum
(6)
All pins
except for
PA10 and
PB12
PA10 and
PB12
All pins
except for
PA10 and
PB12
PA10 and
PB12
(6)
Doc ID 022152 Rev 2
(5)
2.7 V
1.8 V
2.0 V
(~10% order)
V
CMOS ports
CMOS ports
SS
Conditions
TTL ports
V
V
V
≤
≤
≤
≤
IN
IN
IN
V
V
V
V
=
=
DD
DD
DD
=
IN
V
V
5 V
≤
SS
DD
≤
≤
≤
.
V
Table
3.6 V
3.6 V
3.6 V
DD
Table 44
11. All I/Os are CMOS and TTL
5% V
V
V
0.7V
SS
SS
Min
2.0
2.0
30
30
8
8
-
-
-
–0.3
–0.3
DD
DD
are derived from tests
(4)
Electrical characteristics
INJ(PIN)
Typ
200
40
11
40
11
5
-
-
-
-
-
-
-
-
-
-
maximum value.
V
0.3V
DD
3.6
5.2
5.5
Max
0.8
5.5
±1
50
15
50
15
3
-
-
+0.3
(4)
(4)
(4)
DD
99/167
Unit
mV
µA
kΩ
pF
V