STM32F407VG STMicroelectronics, STM32F407VG Datasheet - Page 122

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STM32F407VG

Manufacturer Part Number
STM32F407VG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F407VG

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar

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Electrical characteristics
122/167
General PCB design guidelines
Power supply decoupling should be performed as shown in
depending on whether V
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 49. Power supply and reference decoupling (V
1. V
Figure 50. Power supply and reference decoupling (V
1. V
and LQFP176. When V
and LQFP176. When V
REF+
REF+
and V
and V
REF–
REF–
1 µF // 10 nF
inputs are both available on UFBGA176. V
inputs are both available on UFBGA176. V
REF+
REF+
REF+
and V
and V
Doc ID 022152 Rev 2
is connected to V
REF–
REF–
1 µF // 10 nF
are not available, they are internally connected to V
1 µF // 10 nF
are not available, they are internally connected to V
DDA
REF+
REF+
or not. The 10 nF capacitors should be
V REF+
V DDA
V SSA /V REF-
STM32F
(See note 1)
V
V
(See note 1)
(See note 1)
REF+
REF–
(See note 1)
is also available on LQFP100, LQFP144,
is also available on LQFP100, LQFP144,
STM32F
/V
/V
REF+
REF+
Figure 49
DDA
SSA
STM32F405xx, STM32F407xx
not connected to
connected to
or
ai17535
Figure
ai17536
DDA
DDA
V
DDA
50,
and V
and V
V
DDA
)
SSA
SSA
)
.
.

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