ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 148

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

Electrical characteristics
24.8.5
24.8.6
148/188
Direct drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is
disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by
the input clock signal on XTAL1 pin.
The frequency of CPU clock (f
low time of f
input clock f
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value
can be calculated by the following formula:
For two consecutive TCLs, the deviation caused by the duty cycle of f
so the duration of 2TCL is always 1/f
The minimum value TCL
of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
The address float timings in Multiplexed bus mode (t
TCL (TCL
Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
Oscillator watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F273Z4. This feature is used for
safety operation with external crystal oscillator (available only when using direct drive mode
with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the
frequency of the external crystal oscillator). This watchdog oscillator operates as following.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.
max
XTAL
CPU
= 1/f
.
(i.e. the duration of an individual TCL) is defined by the duty cycle of the
XTAL
x DC
min
has to be used only once for timings that require an odd number
max
CPU
TCL min
) instead of TCL
) directly follows the frequency of f
XTAL
DC
2TCL
=
=
.
1 f ⁄
duty cycle
=
XTALl
1 f XTAL
⁄
Min.
xlDC min
11
and t
45
) use the maximum duration of
XTAL
XTAL
so the high and
is compensated,
ST10F273Z4