FDMF6707C Fairchild Semiconductor, FDMF6707C Datasheet
FDMF6707C
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FDMF6707C Summary of contents
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... The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, integrated MOSFET plus driver power stage solution synchronous buck DC-DC applications. The FDMF6707C integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm PQFN package. With an integrated approach, the complete switching ...
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... VCIN DISB# 10µA V CIN R UP_PWM Input PWM 3- State Logic R DN_PWM THWN# Temp. Sense CGND © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 VDRV VCIN VIN R BOOT DISB# BOOT PWM FDMF6707C PHASE SMOD# VSWH THWN# PGND CGND Figure 1. Typical Application Circuit VDRV ...
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... LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 Figure 4. Top View Description 3 www.fairchildsemi.com ...
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... MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 Parameter Referenced to CGND Referenced to CGND ...
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... High-Level Input Voltage IH_SMOD V Low-Level Input Voltage IL_SMOD I Pull-Up Current PLU t Propagation Delay PD_SLGLL t Propagation Delay PD_SHGLH © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0 5V, and T = +25°C unless otherwise noted. CIN DRV A Condition PWM=LOW or HIGH or Float Q VCIN VDRV ...
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... Delay Exiting 3-State Propagation t PD_TSGLH Delay Boot Diode V Forward-Voltage Drop F V Breakdown Voltage R © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 (Continued 5V, and T = +25°C unless otherwise noted. CIN DRV A Condition I =5mA PLD SW=0V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH ...
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... Timing Diagram V IH_PWM PWM VSWH VSWH t PD PHGLL t D_DEADON © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 90% 1.0V 10 PLGHL Figure 5. PWM Timing Diagram 7 V IL_PWM 10% 90% 1.2V t D_TIMEOUT ( 250ns Timeout) 2.2V t D_DEADOFF www.fairchildsemi.com ...
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... Module Switching Frequency, f Figure 8. Power Loss vs. Switching Frequency 1. 30A 300kHz OUT SW 1.05 1.00 0.95 0.90 4.50 4.75 5.00 Driver Supply Voltage, V Figure 10. Power Loss vs. Driver Supply Voltage © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 =1.0V, V =5V, V =5V, L =320nH, T CIN DRV OUT 1MHz 300kHz ...
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... Driver Supply Current vs. Driver Supply Voltage 4 25° IH_PWM 3.5 3.0 V HIZ_PWM 2.5 2.0 1.5 1.0 0.5 4.50 4.75 5.00 Driver Supply Voltage, V Figure 16. PWM Thresholds vs. Driver Supply Voltage © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 (Continued) =1.0V, V =5V, V =5V, L =320nH, T CIN DRV OUT 50 = 300kHz 325 375 425 ...
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... CIN -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -50 - Driver IC Junction Temperature, T Figure 20. SMOD# Pull-Up Current vs. Temperature 2 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 4.50 4.75 Driver Supply Voltage, V Figure 22. Disable Thresholds vs. Temperature © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 (Continued) =1.0V, V =5V, V =5V, L =320nH, T CIN DRV OUT 2.0 1.9 1.8 1.7 1.6 1.5 V IL_SMOD 1.4 1.3 -50 5.25 5.50 (V) CIN Figure 19. 2.00 1.90 1.80 1.70 1.60 1.50 1. 100 ...
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... PWM input goes from three-state to LOW, the low- side MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on, as illustrated in Figure 25. The FDMF6707C design allows for short propagation delays when exiting the three-state window (see Electrical Characteristics). ...
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... LS V PD_SHGLH GS IH_SMOD © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 turns off after a propagation delay (t Once the VSWH pin falls below ~2 ...
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... VSWH GL 90% 1. PD_PLGHL PD_PHGLL t t D_DEADOFF D_DEADON © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 Table 2. DISB Note: 4. The SMOD feature is intended to have low propagation delay between the SMOD signal and the low-side FET V diode emulation on a cycle-by-cycle basis. ...
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... Input OFF ON Open - Drain Output © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 VCIN Filter ), a local ceramic The VDRV pin provides power to the gate drive of the CIN high-side and low-side power MOSFETs. In most cases, VDRV can be connected directly to VCIN, which supplies power to the logic circuitry of the gate driver ...
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... DrMOS cooling acceptable noise emission output inductor should be located close to the FDMF6707C to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. ® 4. PowerTrench MOSFETs are used in the output stage ...
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... Top View © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 Figure 29. PCB Layout Example 16 Bottom View www.fairchildsemi.com ...
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... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 B PIN#1 INDICATOR 6. ...
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... Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.1 18 www.fairchildsemi.com ...