FDMF6707C Fairchild Semiconductor, FDMF6707C Datasheet - Page 11

• Manufacturer Part Number: FDMF6707C
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FDMF6707C • Rev. 1.0.1
THWN#
Logic
State
Functional Description
The FDMF6707C is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1MHz.
VCIN and Disable (DISB#)
The VCIN pin is monitored by an under-voltage lockout
(UVLO) circuit. When V
is enabled. When V
disabled (GH, GL=0). The driver can also be disabled by
pulling the DISB# pin LOW (DISB# < V
holds both GL and GH LOW regardless of the PWM
input state. The driver can be enabled by raising the
DISB# pin voltage HIGH (DISB# > V
Table 1.
Note:
3.
Thermal Warning Flag (THWN#)
The FDMF6707C provides a thermal warning flag
(THWN#) to advise of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN# output returns to high-
impedance state once the temperature falls to the reset
temperature (135°C). The THWN# output requires a
pull-up resistor, which can be connected to VCIN.
THWN# does NOT disable the DrMOS module.
UVLO DISB#
0
1
1
1
DISB# internal pull-down current source is 10µA.
HIGH
LOW
Open
UVLO and Disable Logic
Figure 24.
X
0
1
Normal
Operation
135°C Reset
Temperature
CIN
T
CIN
J_driver IC
falls below ~2.7V, the driver is
THWN Operation
Enabled (See Table 2)
rises above ~3.1V, the driver
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Driver State
150°C
Activation
Temperature
IH_DISB
).
Thermal
Warning
IL_DISB
), which
11
Three-State PWM Input
The FDMF6707C incorporates a three-state 5V PWM
input gate drive design. The three-state gate drive has
both logic HIGH level and LOW level, along with a
three-state shutdown window. When the PWM input
signal enters and remains within the three -state window
for a defined hold-off time (t
are pulled LOW. This feature enables the gate drive to
shut down both high-and low-side MOSFETs to support
features such as phase shedding, a common feature on
multi-phase voltage regulators.
Exiting Three-State Condition
When
FDMF6707C design follows the PWM input command. If
the PWM input goes from three-state to LOW, the low-
side MOSFET is turned on. If the PWM input goes from
three-state to HIGH, the high-side MOSFET is turned
on, as illustrated in Figure 25. The FDMF6707C design
allows for short propagation delays when exiting the
three-state window (see Electrical Characteristics).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced low R
for GL is internally connected between VDRV and
CGND. When the driver is enabled, the driver's output is
180° out of phase with the PWM input. When the driver
is disabled (DISB#=0V), GL is held LOW.
High-Side Driver
The high-side driver is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstrap capacitor (C
held at PGND, allowing C
through the internal diode. When the PWM input goes
HIGH, GH begins to charge the gate of the high-side
MOSFET (Q1). During this transition, the charge is
removed from C
As Q1 turns on, V
pin to V
enhancement for Q1. To complete the switching cycle,
Q1 is turned off by pulling GH to V
recharged to V
output is in-phase with the PWM input. The high-side
gate is held LOW when the driver is disabled or the
PWM signal is held within the three-state window for
longer than the three-state hold-off time, t
exiting
IN
+ V
DRV
BOOT
a
BOOT
DS(ON)
SWH
valid
when V
, which provides sufficient V
and delivered to the gate of Q1.
BOOT
rises to V
N-channel MOSFET. The bias
D_HOLD-OFF
three-state
). During startup, V
BOOT
SWH
IN
falls to PGND. GH
to charge to V
, forcing the BOOT
SWH
), both GL and GH
. C
condition,
D_HOLD-OFF
BOOT
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is then
SWH
.
DRV
the
GS
is