MT9VDDF3272G-40B Micron Semiconductor Products, MT9VDDF3272G-40B Datasheet - Page 15

• Manufacturer Part Number: MT9VDDF3272G-40B
• Description: 256mb, 512mb X72, Ecc, Sr Pc3200 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

Figure 6:
Read Latency
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72_2.fm - Rev. C 7/05 EN
CAS Latency Diagram
The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 3, 2.5, or
2 clocks, as shown in Figure 6, CAS Latency Diagram.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 6, CAS Latency (CL)
Table, indicates the operating frequencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
COMMAND
COMMAND
COMMAND
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
256MB, 512MB: (x72, ECC, SR) PC3200 184-Pin DDR RDIMM
READ
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
15
NOP
NOP
NOP
T1
T1
T1
CL = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
NOP
NOP
T2
T2
T2n
T2n
T2n
DON’T CARE
Mode Register Definition
T3
NOP
NOP
NOP
T3
T3
©2003 Micron Technology, Inc. All rights reserved.
T3n
T3n
T3n