MT9VDDF3272G-40B Micron Semiconductor Products, MT9VDDF3272G-40B Datasheet - Page 16

• Manufacturer Part Number: MT9VDDF3272G-40B
• Description: 256mb, 512mb X72, Ecc, Sr Pc3200 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

Operating Mode
Extended Mode Register
DLL Enable/Disable
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72_2.fm - Rev. C 7/05 EN
The normal operating mode is selected by issuing a MODE REGISTER SET command
with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required
by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER
command is issued to reset the DLL, it should always be followed by a LOAD MODE
REGISTER command to select normal operating mode.
All other combinations of values for A7–A12 are reserved for future use and/or test
modes. Test modes and reserved states should not be used because unknown operation
or incompatibility with future versions may result.
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable and output drive strength.
These functions are controlled via the bits shown in Figure 7, Extended Mode Register
Definition Diagram. The extended mode register is programmed via the LOAD MODE
REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the device loses power. The enabling
of the DLL should always be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all device banks are idle and no bursts
are in progress, and the controller must wait the specified time before initiating any sub-
sequent operation. Violating either of these requirements could result in unspecified
operation.
The DLL must be enabled for normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. When the device exits self refresh mode, the DLL
is enabled automatically. Any time the DLL is enabled, 200 clock cycles with CKE HIGH
must occur before a READ command can be issued.
256MB, 512MB: (x72, ECC, SR) PC3200 184-Pin DDR RDIMM
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Extended Mode Register
©2003 Micron Technology, Inc. All rights reserved.