MT9VDDF3272G-40B Micron Semiconductor Products, MT9VDDF3272G-40B Datasheet - Page 25

• Manufacturer Part Number: MT9VDDF3272G-40B
• Description: 256mb, 512mb X72, Ecc, Sr Pc3200 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72_2.fm - Rev. C 7/05 EN
16.
17. The Don’t Care state after completion of the postamble means that the DQS-driven
18. This is not a device limit. The device will operate with a negative value, but system
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
20. MIN (
21. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. How-
22. The valid data window is derived by achieving other specifications:
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
25. To maintain a valid level, the transitioning edge of the input must:
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
28. V
29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
30.
31. READs and WRITEs with auto precharge are not allowed to be issued until
t
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
signal should either be high, low, or high-Z, and that any signal transistions within the
input switching region must follow valid input requirements. If DQS transactions
high, above V
prior to
performance could be degraded due to bus turnaround.
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on
minimum absolute value for the respective parameter.
ments is the largest multiple of
ever, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst
refreshing or posting by the DRAM controller greater than eight refresh cycles is not
allowed.
t
tional with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio.
during REFRESH command period (
standby).
the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to
4V/ns, functionality is uncertain. For -40B, slew rates must be ≥ 0.5 V/ns.
the same amount.
t
device CK and CK# inputs, collectively during bank active.
can be satisfied prior to the internal precharge command being issued.
HZ and
DQSQ, and
HP min is the lesser of
b. Reach at least the target AC level.
a. Sustain a constant slew rate from the current AC level through to the target AC
c. After the AC target level is reached, continue to maintain at least the target DC
DD
level, V
level, V
must not vary more than 4 percent if CKE is not active while any bank is active.
t
RC or
t
DQSH (MIN).
t
256MB, 512MB: (x72, ECC, SR) PC3200 184-Pin DDR RDIMM
LZ transitions occur in the same access time windows as valid data transi-
t
DS and
IL
IL
t
t
RFC) for I
QH (
(AC) or V
(DC) or V
IH
(DC) (MIN), then it must not transition low, below V
t
t
QH =
DH for each 100mv/ns reduction in slew rate. If slew rate exceeds
IH
DD
IH
t
(AC).
(DC).
HP -
measurements is the smallest multiple of
t
CL minimum and
25
t
QHS). The data valid window derates directly porpor-
t
CK that meets the maximum absolute value for
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC [MIN]) else CKE is LOW (i.e., during
t
CH minimum actually applied to the
t
DQSS.
t
RAS (MAX) for I
©2003 Micron Technology, Inc. All rights reserved.
t
CK that meets the
IH
DD
t
(DC) (MIN),
HP (
t
RAS(MIN)
measure-
Notes
t
CK/2),
t
RAS.