MT9VDDF3272G-40B Micron Semiconductor Products, MT9VDDF3272G-40B Datasheet - Page 27

• Manufacturer Part Number: MT9VDDF3272G-40B
• Description: 256mb, 512mb X72, Ecc, Sr Pc3200 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72_2.fm - Rev. C 7/05 EN
34. The voltage levels used are derived from a minimum V
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slowest JEDEC operating frequency of 83
41. For -40B, I
42. Random addressing changing and 50 percent of data changing at every transfer.
43. Random addressing changing and 100 percent of data changing at every transfer.
44. CKE must be active (high) during the entire time a refresh command is executed.
45. I
46. Whenever the operating frequency is altered, not including jitter, the DLL is required
47. Leakage number reflects the worst case leakage possible through the module pin, not
48. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic
49. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz.
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
not be greater than 1/3 of the cycle rate. V
width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
t
prevail over
t
but specify when the device output is no longer driving (
(
Alternatively, V
provided a minimum of 42Ω of series resistance is used between the V
the input pin.
MHz. As such, future die may not reflect this option.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until
I
remain stable. Although I
to be reset. This is followed by 200 clock cycles (before READ commands).
what each memory device contributes.
low.
Any noise above 20MHz at the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV.
HZ (MAX) will prevail over
RPST end point and
DD
DD
t
IH
DD
RPRE).
2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
2Q is similar to I
overshoot: V
and V
256MB, 512MB: (x72, ECC, SR) PC3200 184-Pin DDR RDIMM
DD
DDQ
t
DQSCK (MIN) +
3N is specified to be 35mA per DDR SDRAM device at 100 MHz.
must track each other.
TT
IH
may be 1.35V maximum during power up, even if V
(MAX) = V
DD
t
RPRE begin point are not referenced to a specific voltage level
DDQ
2F except I
DD
27
, V
2F, I
DDQ
t
DQSCK (MAX) +
t
RPRE (MAX) condition.
TT
DD
, and V
+ 1.5V for a pulse width ≤ 3ns and the pulse width can
2N, and I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
2Q specifies the address and control inputs to
REF later.
REF
IL
must be equal to or less than V
DD
undershoot: V
t
2Q are similar, I
RPST (MAX) condition.
DD
level and the referenced test
IL
©2003 Micron Technology, Inc. All rights reserved.
t
RPST), or begins driving
(MIN) = -1.5V for a pulse
DD
2F is “worst case.”
DD
t
TT
LZ (MIN) will
/V
supply and
DDQ
DD
Notes
+ 0.3V.
are 0V,