MT9VDDF3272G-40B Micron Semiconductor Products, MT9VDDF3272G-40B Datasheet - Page 18

• Manufacturer Part Number: MT9VDDF3272G-40B
• Description: 256mb, 512mb X72, Ecc, Sr Pc3200 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

Commands
Table 7:
Table 8:
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72_2.fm - Rev. C 7/05 EN
name (function)
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or
reserved
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
Notes: 1. DESELECT and NOP are functionally interchangeable.
Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen-
eral reference of available commands. For a more detailed description of commands and
operations, refer to the 256Mb or 512Mb DDR SDRAM component data sheets.
2. BA0–BA1 provide device bank address and A0–A12 provide row address.
3. BA0–BA1 provide device bank address; A0–A9 (256MB) or A0–A9, A11 (512MB )provide
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10
LOW disables the auto precharge feature.
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
banks are precharged and BA0–BA1 are “Don’t Care.”
except for CKE.
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0–BA1 are reserved). A0–A12 provide the op-code to be written to the selected
mode register.
256MB, 512MB: (x72, ECC, SR) PC3200 184-Pin DDR RDIMM
18
CS#
H
L
L
L
L
L
L
L
L
RAS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
CAS# WE#
X
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
L
L
Bank/Row
Address
Bank/Col
Bank/Col
Op-Code
©2003 Micron Technology, Inc. All rights reserved.
Code
X
X
X
X
DM
H
L
Commands
Notes
6, 7
1
1
2
3
3
4
5
8
Valid
DQs
X