MT9VDDF3272G-40B Micron Semiconductor Products, MT9VDDF3272G-40B Datasheet - Page 24

• Manufacturer Part Number: MT9VDDF3272G-40B
• Description: 256mb, 512mb X72, Ecc, Sr Pc3200 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

Notes
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72_2.fm - Rev. C 7/05 EN
10. I
11. This parameter is sampled. V
12. For slew rates < 1 V/ns and greater ≥ 0.5 V/ns. If slew rate is < 0.5 V/ns, timing must be
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured at the timing reference point indicated in
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,
6. V
7. V
8. I
9. Enables on-chip refresh and address counters.
Output
(V
OUT
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
ment, but input timing is still referenced to V
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1V/ns in the range between V
the receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
the DC level of the same. Peak-to-peak noise (non-common mode) on V
exceed ±2 percent of the DC value. Thus, from V
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest V
resistors, is expected to be set equal to V
of V
with minimum cycle time at CL = 3 for -40B with the outputs open.
the defined cycle rate.
MHz, T
with I/O pins, reflecting the fact that they are matched in loading.
derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from
500mV/ns, while
uncertain. For -40B, slew rates must be ≥ 0.5 V/ns.
which CK and CK# cross; the input reference level for signals other than CK/CK# is
V
before V
Note 3, is V
DD
DD
REF
REF
TT
)
REF
specifications are tested after the device is properly initialized, and is averaged at
is not applied directly to the device. V
is dependent on output loading and cycle rates. Specified values are obtained
.
is expected to equal V
V
TT
.
A
50
REF
30pF
Reference
Point
= 25°C, V
REF
256MB, 512MB: (x72, ECC, SR) PC3200 184-Pin DDR RDIMM
Ω
TT
stabilizes, CKE ≤ 0.3 x V
.
by-pass capacitor.
DD
OUT
t
IH is unaffected. If slew rate exceeds 4.5 V/ns, functionality is
tests may use a V
DD
(
DC
, and electrical AC and DC characteristics may be conducted
) = V
24
DDQ
SS
.
DD
DDQ
/2 of the transmitting device and to track variations in
= +2.5V ±0.2V, V
/2, V
DDQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
-to-V
OUT
IL
is recognized as LOW.
(
REF
AC
REF
TT
(peak to peak) = 0.2V. DM input is grouped
) and V
IH
and must track variations in the DC level
REF
is a system supply for signal termination
stabilizes. Exception: during the period
swing of up to 1.5V in the test environ-
(or to the crossing point for CK/CK#),
DDQ
DDQ
IH
(
/2, V
AC
= +2.5V ±0.2V, V
).
REF
©2003 Micron Technology, Inc. All rights reserved.
is allowed ±25mV for DC
REF
= V
REF
SS
may not
, f = 100
Notes