MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 117

• Manufacturer Part Number: MC56F836
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

6.5.5
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$D01D.
6.5.6
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see
Table 2-2
6.5.6.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
This bit controls the pull-up resistors on the FAULTA3 pin.
6.5.6.3
This bit controls the pull-up resistors on the CAN_RX pin.
6.5.6.4
This bit controls the pull-up resistors on the EMI_MODE pin.
Note:
Freescale Semiconductor
Preliminary
Base + $8
RESET
Write
Read
Base + $7
RESET
Read
Write
to identify which pins can deactivate the internal pull-up resistor.
Least Significant Half of JTAG ID (SIM_LSH_ID)
SIM Pull-up Disable Register (SIM_PUDR)
In this package, this input pin is double-bonded with the adjacent V
changed to a 1 in order to reduce power consumption.
Reserved—Bit 15
PWMA1—Bit 14
CAN—Bit 13
EMI_MODE—Bit 12
15
0
0
15
PWMA1
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
1
1
14
0
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
14
1
1
CAN
13
0
13
0
0
MODE
EMI_
12
0
12
1
1
RESET
11
0
56F8365 Technical Data, Rev. 7
11
0
0
IRQ
10
0
10
0
0
XBOOT PWMB PWMA0
Figure
9
0
9
0
0
6-8) corresponds to a functional group of pins. See
8
0
8
0
0
7
0
7
0
0
6
0
0
6
0
0
CTRL
5
0
0
5
0
SS
pin and this bit should be
4
1
1
4
0
0
JTAG
3
3
0
1
1
2
1
1
2
0
0
Register Descriptions
1
0
0
1
0
0
0
1
1
0
0
0
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