MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 15

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MC56F836

Manufacturer Part Number
MC56F836
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8365 and 56F8165 are organized into functional groups, as detailed
in
present on a pin.
Freescale Semiconductor
Preliminary
Table 2-1
1. If the on-chip regulator is disabled, the V
2. Alternately, can function as Quad Timer pins or GPIO
3. Pins in this section can function as Quad Timer, SPI 1, orGPIO
4. EMI not functional in these packages; use as GPIO pins.
Note: See
Power (V
Power Option Control
Ground (V
Supply Capacitors
PLL and Clock
Bus Control
Interrupt and Program Control
Pulse Width Modulator (PWM) Ports
Serial Peripheral Interface (SPI) Port 0
Serial Peripheral Interface (SPI) Port 1
Quadrature Decoder Port 0
Quadrature Decoder Port 1
Serial Communications Interface (SCI) Ports
CAN Ports
Analog-to-Digital Converter (ADC) Ports
Timer Module Ports
JTAG/Enhanced On-Chip Emulation (EOnCE)
Temperature Sense
Dedicated GPIO ( Address Bus = 11; Data Bus = 4
and as illustrated in
Table 1-1
DD
SS
or V
or V
DDA
SSA
1
for 56F8165 functional differences.
& V
)
)
PP
Functional Group
Table 2-1 Functional Group Pin Allocations
2
3
Figure
56F8365 Technical Data, Rev. 7
CAP
2-1. In
pins serve as 2.5V V
Table
4
)
2-2, each table row describes the signal or signals
DD_CORE
power inputs
56F8365
Number of Pins in Package
26
21
28
9
1
6
6
4
6
4
4
4
4
4
2
6
5
1
56F8165
13
21
28
9
1
6
6
4
6
4
4
4
4
4
4
5
Introduction
15

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