MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 24

• Manufacturer Part Number: MC56F836
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

24
(GPIOD7)
Signal
Name
RXD1
TMS
TDO
TCK
TDI
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Pin No.
115
116
117
118
41
Schmitt
Schmitt
Schmitt
Output
Output
Input/
Type
Input
Input
Input
Input
pulled high
pulled high
pulled low
internally
internally
internally
disabled,
pull-up is
output is
enabled
In reset,
enabled
During
56F8365 Technical Data, Rev. 7
pull-up
Reset
Input,
Input,
Input,
Input,
State
Receive Data — SCI1 receive data input
Port D GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the
JTAG/EOnCE port. The pin is connected internally to a pull-down
resistor.
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note:
Test Data Input — This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Always tie the TMS pin to V
Signal Description
DD
through a 2.2K resistor.
Freescale Semiconductor
Preliminary