MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 4

• Manufacturer Part Number: MC56F836
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 5
Part 2: Signal/Connection Descriptions . . . 15
Part 3: On-Chip Clock Synthesis (OCCS) . 35
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 37
Part 5: Interrupt Controller (ITCN) . . . . . . . 79
Part 6: System Integration Module (SIM) . 111
Part 7: Security Features . . . . . . . . . . . . . 130
4
1.1. 56F8365/56F8165 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment. . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2. External Clock Operation . . . . . . . . . . . . . . 35
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2. Program Map. . . . . . . . . . . . . . . . . . . . . . . . 38
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 40
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 44
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 46
4.7. Peripheral Memory Mapped Registers . . . . 47
4.8. Factory Programmed Memory . . . . . . . . . . 79
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3. Functional Description . . . . . . . . . . . . . . . . . 80
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 82
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 82
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 83
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 111
6.4. Operating Mode Register . . . . . . . . . . . . . 112
6.5. Register Descriptions . . . . . . . . . . . . . . . . 113
6.6. Clock Generation Overview . . . . . . . . . . . 128
6.7. Power-Down Modes Overview . . . . . . . . . 128
6.8. Stop and Wait Mode Disable Function . . . 129
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.1. Operation with Security Enabled . . . . . . . 130
7.2. Flash Access Blocking Mechanisms . . . . . 130
Table of Contents
56F8365 Technical Data, Rev. 7
Part 8: General Purpose Input/Output
Part 9: Joint Test Action Group (JTAG) . . 138
Part 10: Specifications. . . . . . . . . . . . . . . . 138
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 166
Part 12: Design Considerations . . . . . . . . 171
Part 13: Ordering Information . . . . . . . . . . 171
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 133
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 133
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . 133
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 138
10.1. General Characteristics. . . . . . . . . . . . . . 138
10.2. DC Electrical Characteristics. . . . . . . . . . 144
10.3. AC Electrical Characteristics . . . . . . . . . . 148
10.4. Flash Memory Characteristics . . . . . . . . . 149
10.5. External Clock Operation Timing . . . . . . 149
10.6. Phase Locked Loop Timing. . . . . . . . . . . 150
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 150
10.8. Reset, Stop, Wait, Mode Select,
10.9. Serial Peripheral Interface (SPI) Timing . . 153
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . 156
10.11. Quadrature Decoder Timing . . . . . . . . . . 157
10.12. Serial Communication Interface
10.13. Controller Area Network (CAN) Timing . 158
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 159
10.15. Analog-to-Digital Converter
10.16. Equivalent Circuit for ADC Inputs . . . . . . 163
10.17. Power Consumption . . . . . . . . . . . . . . . . 164
11.1. 56F8365 Package and Pin-Out
11.2. 56F8165 Package and Pin-Out
12.1. Thermal Design Considerations . . . . . . . . 171
12.2. Electrical Design Considerations . . . . . . . 171
12.3. Power Distribution and I/O Ring
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 133
and Interrupt Timing . . . . . . . . . . 151
(SCI) Timing . . . . . . . . . . . . . . . . 158
(ADC) Parameters . . . . . . . . . . . 160
Information . . . . . . . . . . . . . . . . . . 166
Information . . . . . . . . . . . . . . . . . 168
Implementation . . . . . . . . . . . . . . 171
Freescale Semiconductor
Preliminary