P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 113

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

Note:
Note:
MCLK
nWAIT
ph2
nMREQ/
SEQ
A[31:0]
MCLK
ABORT
nRESET
nFIQ, nIRQ
Tirs, Trs guarantee recognition of the interrupt (or reset) source by the corresponding clock edge.
Tirm, Trh guarantee non-recognition by that clock edge. These inputs may be applied fully
asynchronously where the exact cycle of recognition is unimportant.
The ARM core is not clocked by the HIGH phase of MCLK enveloped by nWAIT . Thus, during the
cycles shown, nMREQ and SEQ change once, during the first LOW phase of MCLK , and A[31:0]
change once, during the second HIGH phase of MCLK . For reference, ph2 is shown. This is the
internal clock from which the core times all its activity. This signal is included to show how the high
phase of the external MCLK has been removed from the internal core clock.
T
msd
T
clkl
T
ws
Figure 45: Exception Timing
Figure 46: Clock Timing
T
rs
T
T
clkh
abts
T
wh
T
T
rh
abth
T
irs
AC Parameters
T
addr
T
irm
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