P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 15

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). Many FIQ programs will not need
to save any registers. User mode, IRQ mode, Supervisor mode, Abort mode and Undefined mode each have
two banked registers mapped to R13 and R14. The two banked registers allow these modes to each have a
private stack pointer and link register. Supervisor, IRQ, Abort and Undefined mode programs which
require more than these two banked registers are expected to save some or all of the caller's registers (R0 to
R12) on their respective stacks. They are then free to use these registers which they will restore before
returning to the caller. In addition there are also five SPSRs (Saved Program Status Registers) which are
loaded with the CPSR when an exception occurs. There is one SPSR for each privileged mode. Thus the
CPSR of the calling mode can be easily restored when the current (privileged) mode is exited.
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
User32
CPSR
R0
R1
R2
R3
R4
R5
R6
R7
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R15 (PC)
SPSR_fiq
FIQ32
CPSR
General Registers and Program Counter
Program Status Registers
Figure 3: Register Organisation
Supervisor32
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_svc
R14_svc
R15 (PC)
SPSR_svc
CPSR
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_abt
R14_abt
R15 (PC)
SPSR_abt
Abort32
CPSR
Programmer's Model
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_irq
R14_irq
R15 (PC)
SPSR_irq
IRQ32
CPSR
Undefined32
SPSR_und
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_und
R14_und
R15 (PC)
CPSR
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