P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 18

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
To return normally from IRQ, use SUBS PC,R14_irq,#4 which will restore both the PC and the CPSR and
resume execution of the interrupted code. R14_fiq is a symbol for the register R14 and if used needs to be
declared in the users application program.
3.4.3 Abort
An ABORT can be signalled by the external ABORT input. ABORT indicates that the current memory
access cannot be completed. For instance, in a virtual memory system the data corresponding to the current
address may have been moved out of memory onto a disc, and considerable processor activity may be
required to recover the data before the access can be performed successfully. ARM60 checks for ABORT
during memory access cycles. When successfully aborted ARM60 will respond in one of two ways:
(1)
(2)
When either a prefetch or data abort occurs, ARM60 performs the following:
(1)
(2)
(3)
To return after fixing the reason for the abort, use SUBS PC,R14_abt,#4 (for a prefetch abort) or SUBS
PC,R14_abt,#8 (for a data abort). This will restore both the PC and the CPSR and retry the aborted
instruction. R14_fiq is a symbol for the register R14 and if used needs to be declared in the users application
program.
The abort mechanism allows a demand paged virtual memory system to be implemented when suitable
memory management software is available. The processor is allowed to generate arbitrary addresses, and
when the data at an address is unavailable the MMU signals an abort. The processor traps into system
14
(a) Single data transfer instructions (LDR, STR) are aborted as though the instruction had not executed
(b) The swap instruction (SWP) is aborted as though it had not executed, though externally the read
(c) Block data transfer instructions (LDM, STM) complete, and if write-back is set, the base is updated.
If the abort occurred during an instruction prefetch (a Prefetch Abort ), the prefetched instruction is
marked as invalid but the abort exception does not occur immediately. If the instruction is not
executed, for example as a result of a branch being taken while it is in the pipeline, no abort will
occur. An abort will take place if the instruction reaches the head of the pipeline and is about to be
executed.
access may take place.
If the instruction would normally have overwritten the base with data (i.e. LDM with the base in
the transfer list), this overwriting is prevented. All register overwriting is prevented after the Abort
is indicated, which means in particular that R15 (which is always last to be transferred) is preserved
in an aborted LDM instruction.
Saves the address of the aborted instruction plus 4 (for prefetch aborts) or 8 (for data aborts) in
R14_abt; saves CPSR in SPSR_abt.
Forces M[4:0]=10111 (Abort mode) and sets the I bit in the CPSR.
Forces the PC to fetch the next instruction from either address 0x0C (prefetch abort) or address 0x10
(data abort).
if the processor is configured for Early Abort. When configured for Late Abort, these instructions
are able to write back modified base registers and the Abort handler must be aware of this.
If the abort occurred during a data access (a Dat a Abort ), the action depends on the instruction type.