P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 33

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

S, I and N are as defined in section 5.1 Cycle types on page 65.
4.4.8 Assembler syntax
(1)
(2)
(3)
where <Op2> is Rm{,<shift>} or,<#expression>
{cond} - two-character condition mnemonic, see Figure 6: Condition Codes
{S} - set condition codes if S present (implied for CMP, CMN, TEQ, TST).
Rd, Rn and Rm are expressions evaluating to a register number.
If <#expression> is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the
expression. If this is impossible, it will give an error.
<shift> is <shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with extend).
<shiftname>s are: ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same code.)
4.4.9 Examples
Data Processing with PC written
Data Processing with register secified shift and PC written
MOV,MVN - single operand instructions
<opcode>{cond}{S} Rd,<Op2>
CMP,CMN,TEQ,TST - instructions which do not produce a result.
<opcode>{cond} Rn,<Op2>
AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC
<opcode>{cond}{S} Rd,Rn,<Op2>
ADDEQ
TEQS
SUB
MOV
MOVS
R2,R4,R5
R4,#3
R4,R5,R7,LSR R2
PC,R14
PC,R14
Instruction Set - TEQ, TST, CMP & CMN
; if the Z flag is set make R2:=R4+R5
; test R4 for equality with 3
; (the S is in fact redundant as the
; assembler inserts it automatically)
; logical right shift R7 by the number in
; the bottom byte of R2, subtract result
; from R5, and put the answer into R4
; return from subroutine
; return from exception and restore CPSR
from SPSR_mode
2S + 1N
2S +1N + 1I
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