P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 13

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

Programmer's Model
3.0 Programmer's Model
ARM60 supports a variety of operating configurations. Some are controlled by inputs and are known as the
hardware configurations . Others may be controlled by software and these are known as operating modes .
3.1 Hardware ConÞguration
The ARM60 processor provides 4 hardware configurations which may be changed while the processor is
running and which are detailed in Chapter 4.0 Instruction Set.
The BIGEND input sets whether the ARM60 treats words in memory as being stored in Big Endian or Little
Endian format. Memory is viewed as a linear collection of bytes numbered upwards from zero. Bytes 0 to
3 hold the first stored word, bytes 4 to 7 the second and so on.
In the Little Endian scheme the lowest numbered byte in a word is considered to be the least significant byte
of the word and the highest numbered byte is the most significant. Byte 0 of the memory system should be
connected to data lines 7 through 0 ( D[7:0] ) in this scheme.
In the Big Endian scheme the most significant byte of a word is stored at the lowest numbered byte and the
least significant byte is stored at the highest numbered byte. Byte 0 of the memory system should therefore
be connected to data lines 31 through 24 ( D[31:24] ).
The LATEABT input sets the processor's behaviour when a data abort exception occurs. It only affects the
behaviour of load/store register instructions and is discussed more fully in Chapter 3.0 Programmer's Model
and Chapter 4.0 Instruction Set .
The other two inputs, PROG32 and DATA32 are used for backward compatibility with earlier ARM
processors (see 13.0 Appendix - Backward Compatibility ) but should normally be set to 1. This configuration
extends the address space to 32 bits, introduces major changes in the programmer's model as described
below and provides support for running existing 26 bit programs in the 32 bit environment. This mode is
recommended for compatibility with future ARM processors and all new code should be written to use
only the 32 bit operating modes.
Because the original ARM instruction set has been modified to accommodate 32 bit operation there are
certain additional restrictions which programmers must be aware of. These are indicated in the text by the
words shall and shall not. Reference should also be made to the ARM Application Notes ÒRules for ARM Code
WritersÓ and ÒNotes for ARM Code WritersÓ available from your supplier.
3.2 Operating Mode Selection
ARM60 has a 32 bit data bus and a 32 bit address bus. The data types the processor supports are Bytes (8
bits) and Words (32 bits), where words must be aligned to four byte boundaries. Instructions are exactly
one word, and data operations (e.g. ADD) are only performed on word quantities. Load and store
operations can transfer either bytes or words.
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