P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 46

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
the modified base is required (W=1). Figure 19: Post-increment addressing, Figure 20: Pre-increment addressing,
Figure 21: Post-decrement addressing and Figure 22: Pre-decrement addressing show the sequence of register
transfers, the addresses used, and the value of Rn after the instruction has completed.
In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial
value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would
have been overwritten with the loaded value.
4.8.3 Address Alignment
The address should normally be a word aligned quantity and non-word aligned addresses do not affect the
instruction. However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by
the memory system.
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Rn
R5
R1
1
3
Figure 19: Post-increment addressing
0x100C
0x1000
0x0FF4
0x100C
0x1000
0x0FF4
Rn
R1
R7
R5
R1
2
4
0x100C
0x1000
0x0FF4
0x100C
0x1000
0x0FF4