IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 10

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

SIGNAL DESCRIPTION
MASTER RESET (MRS1, MRS2)
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, each of the two
FIFO memories of the IDT72V3684/72V3694/72V36104 undergoes a com-
plete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for
at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH
transitions. The Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the associated write and read pointers to the first
location of the memory and forces the Full/Input Ready flag (FFA/IRA, FFB/
IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost-Empty flag (AEA, AEB) LOW and forces the Almost-Full flag (AFA, AFB)
HIGH. A Master Reset also forces the associated Mailbox Flag (MBF1, MFB2)
of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/
Input Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready
to be written to.
latches the values of the Big-Endian (BE) input for determining the order by
which bytes are transferred through Port B. It also latches the values of the
Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost-Full and Almost-
Empty offset programming method.
Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the
FIFO2 Master Reset (MRS2) together with the FIFO1 Master Reset (MRS1)
input latches the value of the Big-Endian (BE) input for Port B and also latches
the values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost-
Full and Almost-Empty offset programming method. (For details see Table 1,
Flag Programming, and the Programming the Almost-Empty and Almost-Full
Flags section). The relevant FIFO Master Reset timing diagram can be found
in Figure 3.
PARTIAL RESET (PRS1, PRS2)
by taking its associated Partial Reset (PRS1, PRS2) input LOW for at least
four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH
transitions. The Partial Reset inputs can switch asynchronously to the clocks.
A Partial Reset initializes the internal read and write pointers and forces the
Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready
flag (EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB)
LOW, and the Almost-Full flag (AFA, AFB) HIGH. A Partial Reset also forces
the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After
a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two write
clock cycles. Then the FIFO is ready to be written to.
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be inconvenient. See
Figure 4 for the Partial Reset timing diagram.
RETRANSMIT (RT1, RT2)
associated Retransmit (RT1) input LOW for at least four Port A Clock (CLKA)
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
unused inputs) must not be left open, rather they must be either HIGH or LOW.
Each of the two FIFO memories of these devices undergoes a limited reset
Whatever flag offsets, programming method (parallel or serial), and timing
The FIFO1 memory of these devices undergoes a Retransmit by taking its
After power up, a Master Reset operation must be performed by providing
A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input
A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the
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and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializes the read pointer of FIFO1 to the first memory location.
Retransmit (RT2) input LOW for at least four Port A Clock (CLKA) and four Port
C Clock (CLKC) LOW-to-HIGH transitions. The Retransmit initializes the read
pointer of FIFO2 to the first memory location.
RT1input is muxed with the PRS1 input, the state of the RTM pin determining
whether this pin performs a Retransmit or Partial Reset. Also, the RT2input is
muxed with the PRS2 input, the state of the RTM pin determining whether this
pin performs a Retransmit or Partial Reset.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— ENDIAN SELECTION
is active, permitting a choice of Big or Little-Endian byte arrangement for data
written to or read from Port B. This selection determines the order by which
bytes (or words) of data are transferred through this port. For the following
illustrations, assume that a byte (or word) bus size has been selected for Port
B. (Note that when Port B is configured for a long word size, the Big-Endian
function has no application and the BE input is a “don’t care”
inputs go from LOW to HIGH will select a Big-Endian arrangement. When data
is moving in the direction from Port A to Port B, the most significant byte (word)
of the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written
to Port B first will be read from Port A as the most significant byte (word) of the
long word; the byte (word) written to Port B last will be read from Port A as
the least significant byte (word) of the long word.
inputs go from LOW to HIGH will select a Little-Endian arrangement. When data
is moving in the direction from Port A to Port B, the least significant byte (word)
of the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written
to Port B first will be read from Port A as the least significant byte (word) of the
long word; the byte (word) written to Port B last will be read from Port A as
the most significant byte (word) of the long word. Refer to Figure 2 for an
illustration of the BE function. See Figure 3 (Master Reset) for the Endian select
timing diagram.
— TIMING MODE SELECTION
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is
HIGH, a HIGH on the BE/FWFT input during the next LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode.
This mode uses the Empty Flag function (EFA, EFB) to indicate whether or
not there are any words present in the FIFO memory. It uses the Full Flag
function (FFA, FFB) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using a formal read operation.
This is a dual purpose pin. At the time of Master Reset, the BE select function
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2)
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)
After Master Reset, the FWFT select function is active, permitting a choice
The FIFO2 memory undergoes a Retransmit by taking its associated
The RTM pin must be HIGH during the time of Retransmit. Note that the
COMMERCIAL TEMPERATURE RANGE
1
.)