IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 29

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
A0-A35
B0-B35
CLKB edge is less than t
SKEW1
W/RA
CLKA
CLKB
W/RB
MBA
CSA
EFA
ENA
MBB
CSB
ENB
FFB
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
LOW
FIFO2 Full
LOW
LOW
LOW
LOW
HIGH
Previous Word in FIFO2 Output Register
t
CLKH
SKEW1
Figure 22. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
t
, then FFB may transition HIGH one CLKB cycle later than shown.
CLK
t
ENS2
t
CLKL
t
t
ENH
SKEW1
t
A
(1)
1
t
CLKH
TM
WITH
t
CLK
29
t
CLKL
2
t
Next Word From FIFO2
WFF
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
Write
t
WFF
t
t
t
ENH
DH
ENH
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