IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 24

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
B0-B35
A0-A35
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
CLKB edge is less than t
CLKA
CLKB
SKEW1
W/RB
WRA
MBA
MBB
CSA
CSB
ENA
EFB
ENB
FFA
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
FIFO1 Empty
HIGH
LOW
LOW
LOW
HIGH
HIGH
Figure 16. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
t
t
SKEW1
ENS2
ENS2
t
DS
, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
W1
t
SKEW1
t
t
t
ENH
ENH
DH
(1)
t
CLKH
1
t
CLK
t
CLKL
TM
WITH
24
t
2
REF
t
CLKH
t
ENS2
t
CLK
t
CLKL
t
REF
t
A
t
ENH
COMMERCIAL TEMPERATURE RANGE
W1
4677 drw18