IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 31

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104.
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35
CLKB
CLKA
B0-B35
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
A0-A35
ENB
AFB
ENA
CLKA edge is less than t
CLKA
W/RA
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will
have valid data (B9-B35 will be indeterminate).
SKEW2
CLKB
W/RB
MBF1
MBA
MBB
CSA
ENA
ENB
CSB
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
[D-(Y2+1)] Words in FIFO2
SKEW2
t
ENS2
, then AFB may transition HIGH one CLKB cycle later than shown.
Figure 26. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
Figure 27. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
t
EN
FIFO1 Output Register
t
t
t
t
t
PAF
t
ENH
ENS2
ENS1
ENS2
ENS1
t
DS
W1
t
MDV
t
t
t
t
DH
t
ENH
ENH
ENH
ENH
t
t
ENS2
PMF
t
PMR
TM
WITH
31
(D-Y2) Words in FIFO2
t
SKEW2
t
ENH
W1 (Remains valid in Mail1 Register after read)
(1)
1
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
ENH
t
PMF
2
t
PAF
t
DIS
4677 drw29
4677 drw28