IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 3

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

Each Mailbox register has a flag (MBF1 and MBF2) to signal when new mail
has been stored.
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array, configures the FIFO for Big- or Little-Endian byte
arrangement and selects serial flag programming, parallel flag programming,
or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024. There
are two Master Reset pins, MRS1 and MRS2.
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
a respective FIFO only the read pointer is reset to the first memory location. A
Retransmit is performed by using the Retransmit Mode, RTM pin in conjunction
with the Retransmit pins RT1 or RT2, for each respective FIFO. Note that the
two Retransmit pins RT1 and RT2 are muxed with the Partial Reset pins.
first word written to an empty FIFO is deposited into the memory array. A read
operation is required to access that word (along with all other words residing
in memory). In the First Word Fall Through mode (FWFT), the first long-word
(36-bit wide) written to an empty FIFO appears automatically on the outputs, no
read operation is required (Nevertheless, accessing subsequent words does
necessitate a formal read request). The state of the BE/FWFT pin during FIFO
operation determines the mode in use.
ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The
EF and FF functions are selected in the IDT Standard mode. EF indicates
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Partial Reset also sets the read and write pointers to the first location of the
Both FIFO's have Retransmit capability, when a Retransmit is performed on
These devices have two modes of operation: In the IDT Standard mode, the
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/
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whether or not the FIFO memory is empty. FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate when
a selected number of words remain in the FIFO memory. AFA and AFB indicate
when the FIFO contains more than a selected number of words.
clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are
two-stage synchronized to the port clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA and AFB are loaded in parallel using
Port A or in serial via the SD input. Five default offset settings are also provided.
The AEA and AEB threshold can be set at 8, 16, 64, 256 or 1,024 locations
from the empty boundary and the AFA and AFB threshold can be set at 8, 16,
64, 256 or 1,024 locations from the full boundary. All these choices are made
using the FS0, FS1 and FS2 inputs during Master Reset.
If Interspersed Parity is selected then during parallel programming of the flag
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit.
at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
inputs) will immediately take the device out of the power down state.
from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available.
They are fabricated using IDT’s high speed, submicron CMOS technology.
Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port
Interspersed Parity can also be selected during a Master Reset of the FIFO.
Two or more devices may be used in parallel to create wider data paths. If,
The IDT72V3684/72V3694/72V36104 are characterized for operation
CC
) is at a minimum. Initiating any operation (by activating control
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