IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 7

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
and CLKB set to f
to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL
HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
The I
With I
100
50
80
70
60
40
30
20
90
10
0
CC(f)
P
where:
N
C
f
o
CC(f)
0
T
L
= V
current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3684/72V3694/72V36104 with CLKA
taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
S
CC
. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected
=
=
=
x I
10
CC
f
T
C
(f) + Σ(C
data
A
L
= 25°C
= 0 pF
= 1/2 f
N
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
output capacitance load
switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (I
L
S
x V
20
CC
2
x fo)
30
V
f
S
CC =
40

Clock Frequency
3.3V
TM
WITH
7
50

MHz
CC
60
) vs. Clock Frequency (f
70
COMMERCIAL TEMPERATURE RANGE
V
CC =
3.6V
S
80
)
V
CC =
3.0V
90
4677 drw03
100