IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 5

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTE:
1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or V
PIN DESCRIPTIONS (CONTINUED)
Symbol
FS1/SEN Flag Offset Select 1/
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
FS0/SD Flag Offset Select 0/
FS2
MBA
MBB
MBF1
MBF2
MRS1
MRS2
PRS1/
RT1
PRS2/
RT2
RTM
SIZE
W/RA
W/RB
(1)
(1)
Serial Data
Serial Enable,
Flag Offset Select 2
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
FIFO2 Master
Reset
Partial Reset/
Retransmit FIFO1
Partial Reset/
Retransmit FIFO2
Retransmit Mode
Bus Size Select
Port-A Write/
Read Select
Port-B Write/
Read Select
Name
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master
Reset, FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three offset
register programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or
1,024), parallel load from Port A, and serial load.
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load
the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset
registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write
stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level
selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port
B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or parallel)
and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and
endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects the
programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-to-
HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read
and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable
flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read
pointer only to the first memory location.
This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read
and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag
settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer
only to the first memory location.
This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on
FIFO1 or FIFO2 respectively.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH
selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port
B. The level of SIZE must be static throughout device operation
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable
TM
WITH
5
CC
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Description
COMMERCIAL TEMPERATURE RANGE